Issued Patents All Time
Showing 351–364 of 364 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6879000 | Isolation for SOI chip with multiple silicon film thicknesses | — | 2005-04-12 |
| 6872606 | Semiconductor device with raised segment | Hao Chen, Fu-Liang Yang, Chenming Hu | 2005-03-29 |
| 6867433 | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors | How-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Fu-Liang Yang, Chenming Hu | 2005-03-15 |
| 6864149 | SOI chip with mesa isolation and recess resistant regions | Hao Chen, Hsun-Chih Tsao, Fu-Liang Yang, Chenming Hu | 2005-03-08 |
| 6864519 | CMOS SRAM cell configured using multiple-gate transistors | Chenming Hu, Fu-Liang Yang | 2005-03-08 |
| 6855990 | Strained-channel multiple-gate transistor | Fu-Liang Yang, Chenming Hu | 2005-02-15 |
| 6855606 | Semiconductor nano-rod devices | Hao Chen, Fu-Liang Yang, Chenming Hu | 2005-02-15 |
| 6844238 | Multiple-gate transistors with improved gate control | Fu-Liang Yang, Chenming Hu | 2005-01-18 |
| 6835967 | Semiconductor diodes with fin structure | Fu-Liang Yang | 2004-12-28 |
| 6830953 | Suppression of MOSFET gate leakage current | Chenming Hu | 2004-12-14 |
| 6812116 | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance | Chien-Chao Huang, Kuo-Nan Yang, Chun-Chieh Lin, Chenming Hu | 2004-11-02 |
| 6720619 | Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices | Hao Chen, Fu-Liang Yang, Chenming Hu | 2004-04-13 |
| 6703271 | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer | Chun-Chieh Lin, Fu-Liang Yang, Chen Ming Hu | 2004-03-09 |
| 6492216 | Method of forming a transistor with a strained channel | Fu-Liang Yang, Chenming Hu | 2002-12-10 |