Issued Patents All Time
Showing 51–75 of 217 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11923297 | Apparatus and methods for generating a circuit with high density routing layout | Wei-An Lai, Shih-Wei Peng, Jiann-Tyng Tzeng | 2024-03-05 |
| 11923301 | Method of manufacturing semiconductor device | Shih-Wei Peng, Hui-Ting Yang, Jiann-Tyng Tzeng | 2024-03-05 |
| 11916077 | Method for routing local interconnect structure at same level as reference metal line | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young +5 more | 2024-02-27 |
| 11916074 | Double rule integrated circuit layouts for a dual transmission gate | Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue | 2024-02-27 |
| 11916070 | Semiconductor structure with nanosheets | Te-Hsin Chiu, Kam-Tou Sio, Shang-Wei Fang, Jiann-Tyng Tzeng | 2024-02-27 |
| 11908852 | Layout designs of integrated circuits having backside routing tracks | Wei-An Lai, Shih-Wei Peng, Jiann-Tyng Tzeng | 2024-02-20 |
| 11893333 | Hybrid sheet layout, method, system, and structure | Shang-Wei Fang, Kam-Tou Sio, Jiann-Tyng Tzeng, Lee-Chung Lu, Yi-Kan Cheng +1 more | 2024-02-06 |
| 11894375 | Semiconductor structure and method of forming the same | Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng | 2024-02-06 |
| 11862561 | Semiconductor devices with backside routing and method of forming same | Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Shih-Wei Peng +1 more | 2024-01-02 |
| 11854786 | Deep lines and shallow lines in signal conducting paths | Wei-An Lai, Te-Hsin Chiu, Shih-Wei Peng, Jiann-Tyng Tzeng, Chia-Tien Wu | 2023-12-26 |
| 11842137 | Integrated circuit and method of manufacturing same | Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng +1 more | 2023-12-12 |
| 11842967 | Semiconductor devices with backside power distribution network and frontside through silicon via | Kam-Tou Sio, Cheng-Chi Chuang, Chia-Tien Wu, Jiann-Tyng Tzeng, Shih-Wei Peng | 2023-12-12 |
| 11797746 | Method of forming semiconductor device having more similar cell densities in alternating rows | Hui-Ting Yang, Jiann-Tyng Tzeng, Lipen Yuan, Wei-An Lai | 2023-10-24 |
| 11783109 | IC device manufacturing method | Shih-Wei Peng, Guo-Huei Wu, Hui-Zhong Zhuang, Jiann-Tyng Tzeng | 2023-10-10 |
| 11769723 | Three dimensional integrated circuit with monolithic inter-tier vias (MIV) | Shih-Wei Peng, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-An Lai | 2023-09-26 |
| 11756876 | Semiconductor devices having power rails and signal tracks arranged in different layer | Wei-An Lai, Jiann-Tyng Tzeng | 2023-09-12 |
| 11755812 | Power structure with power pick-up cell connecting to buried power rail | Shih-Wei Peng, Jiann-Tyng Tzeng | 2023-09-12 |
| 11755808 | Mixed poly pitch design solution for power trim | Shih-Wei Peng, Lipen Yuan, Jiann-Tyng Tzeng | 2023-09-12 |
| 11741288 | Routing-resource-improving method of generating layout diagram, system for same and semiconductor device | Shih-Wei Peng, Jiann-Tyng Tzeng, Jay Yang | 2023-08-29 |
| 11735517 | Integrated circuit including super via and method of making | Kam-Tou Sio, Jiann-Tyng Tzeng | 2023-08-22 |
| 11728269 | Semiconductor device, and associated method and system | Shih-Wei Peng, Jiann-Tyng Tzeng | 2023-08-15 |
| 11720737 | Semiconductor structure, device, and method | Shih-Wei Peng, Jiann-Tyng Tzeng | 2023-08-08 |
| 11688691 | Method of making standard cells having via rail and deep via structures | Cheng-Chi Chuang, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Wayne Lai | 2023-06-27 |
| 11658119 | Backside signal interconnection | Yu-Xuan Huang, Ching-Wei Tsai, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng +6 more | 2023-05-23 |
| 11637066 | Integrated circuit and method for forming the same | Shih-Wei Peng, Cheng-Chi Chuang, Jiann-Tyng Tzeng | 2023-04-25 |