Issued Patents All Time
Showing 51–75 of 161 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11550986 | Inverted integrated circuit and method of forming the same | Pochun Wang, Yu-Jung Chang, Hui-Zhong Zhuang | 2023-01-10 |
| 11544437 | System for designing integrated circuit layout and method of making the integrated circuit layout | Shang-Chih Hsieh, Chun-Fu Chen, Hui-Zhong Zhuang, Hsiang-Jen Tseng | 2023-01-03 |
| 11532586 | Connecting techniques for stacked substrates | Hsiang-Jen Tseng, Wei-Yu Chen, Li-Chun Tien | 2022-12-20 |
| 11526647 | Isolation circuit between power domains | Chi-Yu Lu, Hui-Zhong Zhuang, Jerry Chang Jui Kao, Pin-Dai Sue, Jiun-Jia Huang +2 more | 2022-12-13 |
| 11508661 | Integrated circuit and method of manufacturing same | Pochun Wang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu +6 more | 2022-11-22 |
| 11469321 | Semiconductor device | Ze-Sian Lu, Pin-Dai Sue, Jung-Hsuan Chen, Hui Li | 2022-10-11 |
| 11461528 | Integrated circuit, system for and method of forming an integrated circuit | Jung-Chan Yang, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien +3 more | 2022-10-04 |
| 11437321 | Standard-cell layout structure with horn power and smart metal cut | Ni-Wan Fan, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan +1 more | 2022-09-06 |
| 11409938 | Integrated circuit and method of manufacturing same | Hui-Zhong Zhuang, Li-Chun Tien | 2022-08-09 |
| 11309311 | Methods of resistance and capacitance reduction to circuit output nodes | Po-Chia Lai, Shang-Wei Fang, Meng-Hung Shen, Jiann-Tyng Tzeng, Jung-Chan Yang +1 more | 2022-04-19 |
| 11295055 | Transmission gate structure and method | Shao-Lun Chien, Pin-Dai Sue, Li-Chun Tien, Ting Yu Chen | 2022-04-05 |
| 11239228 | Integrated circuit layout and method of configuring the same | Chung-Te Lin, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien | 2022-02-01 |
| 11227084 | Multi-bit standard cell | Jerry Chang Jui Kao, Hui-Zhong Zhuang, Yung-Chen Chien, Chih-Wei Chang, Xiangdong Chen | 2022-01-18 |
| 11217553 | Connection structure for stacked substrates | Hsiang-Jen Tseng, Wei-Yu Chen, Li-Chun Tien | 2022-01-04 |
| 11182529 | Semiconductor device including power-grid-adapted route-spacing and method for generating layout diagram of same | Li-Chun Tien, Shun Li Chen, Ting Yu Chen, XinYong WANG | 2021-11-23 |
| 11177256 | Odd-fin height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same | Hui-Zhong Zhuang, Chung-Te Lin, Lee-Chung Lu, Li-Chun Tien, Ting Yu Chen | 2021-11-16 |
| 11132488 | Method of modifying cell, system for modifying cell and global connection routing method | Sheng-Hsiung Chen, Jyun-Hao Chang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang | 2021-09-28 |
| 11093684 | Power rail with non-linear edge | Jung-Chan Yang, Hui-Zhong Zhuang, Chi-Yu Lu | 2021-08-17 |
| 11088067 | Semiconductor device and layout design thereof | Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue | 2021-08-10 |
| 11080461 | Method for improved cut metal patterning | Kuang-Ching Chang, Hui-Zhong Zhuang, Jung-Chan Yang | 2021-08-03 |
| 11075164 | Semiconductor device including a conductive feature over an active region | Tung-Heng Hsieh, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien, Sheng-Hsiung Wang | 2021-07-27 |
| 11074390 | Method of designing an integrated circuit and integrated circuit | Chien-Hsing Li, Jung-Chan Yang, Ting Yu Chen | 2021-07-27 |
| 11050415 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2021-06-29 |
| 11048849 | Integrated circuit and method of manufacturing the same | Pochun Wang, Hui-Zhong Zhuang, Yu-Jung Chang | 2021-06-29 |
| 11037957 | Semiconductor structure | Hsueh-Chih Chou, Chia Hao Tu, Sang Hoo Dhong, Lee-Chung Lu, Li-Chun Tien +1 more | 2021-06-15 |