Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12300669 | Backside contact for thermal displacement in a multi-wafer stacked integrated circuit | Hsing-Chih Lin, Min-Feng Kao | 2025-05-13 |
| 12278151 | Semiconductor wafer seal ring having protrusion extending into trench in semiconductor substrate | Ming-Che Lee, Kuo-Ming Wu, Sheng-Chau Chen, Hau-Yi Hsiao, Guanyu Luo +1 more | 2025-04-15 |
| 12218106 | Backside contact to improve thermal dissipation away from semiconductor devices | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu +1 more | 2025-02-04 |
| 12205868 | Oversized via as through-substrate-via (TSV) stop layer | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu | 2025-01-21 |
| 12191282 | Shared pad/bridge layout for a 3D IC | Harry-Hak-Lay Chuang, Wei-Cheng Wu, Wen-Tuo Huang, Chia-Sheng Lin, Wei Chuang Wu +5 more | 2025-01-07 |
| 11756936 | Backside contact to improve thermal dissipation away from semiconductor devices | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu +1 more | 2023-09-12 |
| 11756862 | Oversized via as through-substrate-via (TSV) stop layer | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu | 2023-09-12 |
| 11694997 | Backside contact for thermal displacement in a multi-wafer stacked integrated circuit | Hsing-Chih Lin, Min-Feng Kao | 2023-07-04 |
| 11289455 | Backside contact to improve thermal dissipation away from semiconductor devices | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu +1 more | 2022-03-29 |
| 11282769 | Oversized via as through-substrate-via (TSV) stop layer | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu | 2022-03-22 |
| 11195818 | Backside contact for thermal displacement in a multi-wafer stacked integrated circuit | Hsing-Chih Lin, Min-Feng Kao | 2021-12-07 |