Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9620421 | Metal gate transistor, integrated circuits, systems, and fabrication methods thereof | Chien Chih Ho, Chih-Ping Chao, Hua-Chou Tseng, Chun-Hung Chen, Chia-Yi Su +2 more | 2017-04-11 |
| 9437485 | Method for line stress reduction through dummy shoulder structures | Cheng-Cheng Kuo, Tzu-Chun Lo, Ming-Hsing Tsai, Ken-Yu Chang, Jeng-Shiun Ho +2 more | 2016-09-06 |
| 9397045 | Structure and formation method of damascene structure | Tai-Yen Peng, Chia-Tien Wu | 2016-07-19 |
| 8971014 | Protection structure for metal-oxide-metal capacitor | Wei-Chun Hua, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao, Hua-Chou Tseng | 2015-03-03 |
| 8765600 | Contact structure for reducing gate resistance and method of making the same | Chung-Long Chang, Chih-Ping Chao, Chun-Hung Chen, Hua-Chao Tseng, Harry-Hak-Lay Chuang | 2014-07-01 |
| 8692351 | Dummy shoulder structure for line stress reduction | Cheng-Cheng Kuo, Luke Lo, Minghsing Tsai, Ken-Yu Chang, Jeng-Shiun Ho +2 more | 2014-04-08 |
| 8450200 | Method for stacked contact with low aspect ratio | Chen-Hua Yu, Chen-Nan Yeh, Chih-Hsiang Yao, Wen-Kai Wan | 2013-05-28 |
| 7880303 | Stacked contact with low aspect ratio | Chen-Hua Yu, Chen-Nan Yeh, Chih-Hsiang Yao, Wen-Kai Wan | 2011-02-01 |
| 7135406 | Method for damascene formation using plug materials having varied etching rates | Jian-Hong Lin, Ying-Jen Kao | 2006-11-14 |
| 6577149 | Method and device for addressable failure site test structure | Yih-Yuh Doong, Ching-Hsiang Hsu Charles | 2003-06-10 |
| 6017821 | Chemical-mechanical polishing method for forming plugs | Sen Yang | 2000-01-25 |
| 5635037 | Method of texture by in-situ masking and etching for thin film magnetic recording medium | Jau-Jier Chu, Chung-Yu Ting, Oliver J. Horng, Charles Lin, Mei-Rurng Tseng | 1997-06-03 |