Issued Patents All Time
Showing 151–175 of 261 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11424154 | Buried metal for FinFET device and method | Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young | 2022-08-23 |
| 11409937 | Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same | Wei-Cheng Lin, Hui-Ting Yang, Lipen Yuan, Wei-An Lai | 2022-08-09 |
| 11374005 | Semiconductor structure and method of forming the same | Shih-Wei Peng, Te-Hsin Chiu, Wei-Cheng Lin | 2022-06-28 |
| 11355487 | Layout designs of integrated circuits having backside routing tracks | Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin | 2022-06-07 |
| 11328957 | Semiconductor device and manufacturing method thereof | Shih-Wei Peng, Wei-Cheng Lin | 2022-05-10 |
| 11309311 | Methods of resistance and capacitance reduction to circuit output nodes | Po-Chia Lai, Shang-Wei Fang, Meng-Hung Shen, Ting-Wei Chiang, Jung-Chan Yang +1 more | 2022-04-19 |
| 11309247 | Semiconductor device, and associated method and system | Shih-Wei Peng, Wei-Cheng Lin | 2022-04-19 |
| 11302631 | Integrated circuit cells and related methods | Te-Hsin Chiu, Shih-Wei Peng | 2022-04-12 |
| 11296070 | Integrated circuit with backside power rail and backside interconnect | Shih-Wei Peng, Guo-Huei Wu | 2022-04-05 |
| 11282829 | Integrated circuit with mixed row heights | Kam-Tou Sio, Chung-Hsing Wang, Yi-Kan Cheng | 2022-03-22 |
| 11270936 | Integrated circuit including supervia and method of making | Kam-Tou Sio, Wei-Cheng Lin | 2022-03-08 |
| 11257670 | Method of manufacturing a semiconductor device, and associated semiconductor device and system | Shih-Wei Peng, Chia-Tien Wu | 2022-02-22 |
| 11232248 | Routing-resource-improving method of generating layout diagram and system for same | Shih-Wei Peng, Wei-Cheng Lin, Jay Yang | 2022-01-25 |
| 11222899 | Semiconductor device which includes fins and method of making same | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Kam-Tou Sio +3 more | 2022-01-11 |
| 11222157 | Pin access hybrid cell height design | Kam-Tou Sio | 2022-01-11 |
| 11217528 | Semiconductor structure having buried power rail disposed between two fins and method of making the same | Shih-Wei Peng, Wei-Cheng Lin | 2022-01-04 |
| 11171089 | Line space, routing and patterning methodology | Shih-Wei Peng, Chih-Ming Lai, Wei-Cheng Lin | 2021-11-09 |
| 11159164 | Integrated circuit and method of manufacturing the same | Shih-Wei Peng, Cheng-Chi Chuang, Chih-Ming Lai, Wei-Cheng Lin | 2021-10-26 |
| 11158580 | Semiconductor devices with backside power distribution network and frontside through silicon via | Kam-Tou Sio, Cheng-Chi Chuang, Chia-Tien Wu, Shih-Wei Peng, Wei-Cheng Lin | 2021-10-26 |
| 11152348 | Integrated circuit with mixed row heights | Kam-Tou Sio, Jack Liu, Yi-Chuin Tsai, Shang-Wei Fang, Sing-Kai Huang +1 more | 2021-10-19 |
| 11145678 | Method for manufacturing semiconductor device | Jack Liu, Chih-Liang Chen, CHEW-YUEN YOUNG, Sing-Kai Huang, Ching-Fang Huang | 2021-10-12 |
| 11139245 | Advanced node interconnect routing methodology | Shih-Wei Peng | 2021-10-05 |
| 11133255 | Metal patterning for internal cell routing | Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Wei-Cheng Lin | 2021-09-28 |
| 11133254 | Hybrid power rail structure | Wei-An Lai, Wei-Cheng Lin | 2021-09-28 |
| 11126775 | IC layout, method, device, and system | Shih-Wei Peng, Guo-Huei Wu, Wei-Cheng Lin, Hui-Zhong Zhuang | 2021-09-21 |