Issued Patents All Time
Showing 101–125 of 261 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11842994 | Semiconductor device having staggered gate-stub-size profile and method of manufacturing same | Te-Hsin Chiu, Shih-Wei Peng | 2023-12-12 |
| 11842967 | Semiconductor devices with backside power distribution network and frontside through silicon via | Kam-Tou Sio, Cheng-Chi Chuang, Chia-Tien Wu, Shih-Wei Peng, Wei-Cheng Lin | 2023-12-12 |
| 11817392 | Integrated circuit | Shih-Wei Peng, Chia-Tien Wu | 2023-11-14 |
| 11810811 | Buried metal for FinFET device and method | Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young | 2023-11-07 |
| 11810949 | Semiconductor arrangement and method of making | Shih-Wei Peng | 2023-11-07 |
| 11797746 | Method of forming semiconductor device having more similar cell densities in alternating rows | Wei-Cheng Lin, Hui-Ting Yang, Lipen Yuan, Wei-An Lai | 2023-10-24 |
| 11797745 | Semiconductor device with reduced power and method of manufacturing the same | Shih-Wei Peng, Ching-Yu Huang | 2023-10-24 |
| 11784179 | Structure and method of power supply routing in semiconductor device | Shih-Wei Peng | 2023-10-10 |
| 11783109 | IC device manufacturing method | Shih-Wei Peng, Guo-Huei Wu, Wei-Cheng Lin, Hui-Zhong Zhuang | 2023-10-10 |
| 11769766 | Integrated circuit with mixed row heights | Kam-Tou Sio, Chung-Hsing Wang, Yi-Kan Cheng | 2023-09-26 |
| 11769723 | Three dimensional integrated circuit with monolithic inter-tier vias (MIV) | Shih-Wei Peng, Kam-Tou Sio, Wei-Cheng Lin, Wei-An Lai | 2023-09-26 |
| 11768991 | Pin access hybrid cell height design | Kam-Tou Sio | 2023-09-26 |
| 11756876 | Semiconductor devices having power rails and signal tracks arranged in different layer | Wei-An Lai, Wei-Cheng Lin | 2023-09-12 |
| 11755812 | Power structure with power pick-up cell connecting to buried power rail | Shih-Wei Peng, Wei-Cheng Lin | 2023-09-12 |
| 11755808 | Mixed poly pitch design solution for power trim | Shih-Wei Peng, Lipen Yuan, Wei-Cheng Lin | 2023-09-12 |
| 11741288 | Routing-resource-improving method of generating layout diagram, system for same and semiconductor device | Shih-Wei Peng, Wei-Cheng Lin, Jay Yang | 2023-08-29 |
| 11737254 | Memory device and layout, manufacturing method of the same | Te-Hsin Chiu, Shih-Wei Peng, Wei-An Lai | 2023-08-22 |
| 11735517 | Integrated circuit including super via and method of making | Kam-Tou Sio, Wei-Cheng Lin | 2023-08-22 |
| 11728269 | Semiconductor device, and associated method and system | Shih-Wei Peng, Wei-Cheng Lin | 2023-08-15 |
| 11721576 | Semiconductor devices and methods of manufacturing thereof | Te-Hsin Chiu, Shih-Wei Peng, Wei-An Lai | 2023-08-08 |
| 11720737 | Semiconductor structure, device, and method | Shih-Wei Peng, Wei-Cheng Lin | 2023-08-08 |
| 11715636 | Method of manufacturing a semiconductor device | Shih-Wei Peng, Chia-Tien Wu | 2023-08-01 |
| 11704464 | Integrated circuit including misaligned isolation portions | Shih-Wei Peng, Chih-Ming Lai | 2023-07-18 |
| 11675952 | Integrated circuit, system and method of forming the same | Shih-Wei Peng, Te-Hsin Chiu | 2023-06-13 |
| 11664311 | Method and structure to reduce cell width in semiconductor device | Shih-Wei Peng | 2023-05-30 |