Issued Patents All Time
Showing 51–74 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9865335 | SRAM device capable of working in multiple low voltages without loss of performance | Pankaj Aggarwal, Jui-Che Tsai, Cheng Hung Lee, Chien-Yuan Chen, Hau-Tai Shieh +1 more | 2018-01-09 |
| 9824729 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen +2 more | 2017-11-21 |
| 9762216 | Level shifter circuit using boosting circuit | Mahmut Sinangil, Hsin-Hsin Ko, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2017-09-12 |
| 9666253 | Dual rail memory, memory macro and associated hybrid power supply method | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Hung-Jen Liao, Michael Patrick Clinton | 2017-05-30 |
| 9659603 | Power management circuit for an electronic device | Hektor Huang, Yangsyu Lin, Yu-Hao Hsu, Chia-En Huang, Chen-Lin Yang +2 more | 2017-05-23 |
| 9583181 | SRAM device capable of working in multiple low voltages without loss of performance | Pankaj Aggarwal, Jui-Che Tsai, Cheng Hung Lee, Chien-Yuan Chen, Hau-Tai Shieh +1 more | 2017-02-28 |
| 9489991 | Memory reading circuit, memory device and method of operating memory device | Yangsyu Lin, Hsin-Hsin Ko, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2016-11-08 |
| 9437281 | Negative bitline boost scheme for SRAM write-assist | Wei-jer Hsieh, Yangsyu Lin, Hsiao Wen Lu, Jonathan Tsung-Yung Chang | 2016-09-06 |
| 9324413 | Write assist circuit, memory device and method | Hsin-Hsin Ko, Yangsyu Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2016-04-26 |
| 9324453 | Memory unit and method of testing the same | Wei-jer Hsieh, Hong-Chen Cheng, Yangsyu Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2016-04-26 |
| 9305635 | High density memory structure | Yangsyu Lin, Hsiao Wen Lu, Jonathan Tsung-Yung Chang | 2016-04-05 |
| 9263123 | Memory device and a method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2016-02-16 |
| 9076553 | SPSRAM wrapper | Wei-jer Hsieh, Chien-Kuo Su, Cheng Hung Lee, Tsung-Yung Chang | 2015-07-07 |
| 9070432 | Negative bitline boost scheme for SRAM write-assist | Wei-jer Hsieh, Yangsyu Lin, Hsiao Wen Lu, Jonathan Tsung-Yung Chang | 2015-06-30 |
| 9064550 | Method and apparatus for word line suppression | Jonathan Tsung-Yung Chang, Chien-Kuo Su, Chung-Cheng Chou, Jack Liu | 2015-06-23 |
| 9025356 | Fly-over conductor segments in integrated circuits with successive load devices along a signal path | Hsiao Wen Lu, Wei-jer Hsieh, Chung-Cheng Chou, Jonathan Tsung-Yung Chang | 2015-05-05 |
| 8923078 | Voltage divider control circuit | Yangsyu Lin, Hsin-Hsin Ko, Jonathan Tsung-Yung Chang | 2014-12-30 |
| 8848461 | Memory cell having flexible read/write assist and method of using | Jonathan Tsung-Yung Chang, Kun-Hsi Li | 2014-09-30 |
| 8816403 | Efficient semiconductor device cell layout utilizing underlying local connective features | Jung-Hsuan Chen, May-Hua Chang, Li-Chun Tien | 2014-08-26 |
| 8724420 | SRAM write assist apparatus | Chung-Cheng Chou, Tsung-Yung Chang | 2014-05-13 |
| 8675439 | Bit line voltage bias for low power memory design | Hong-Chen Cheng, Jung-Ping Yang, Cheng Hung Lee, Sang H. Dong, Hung-Jen Liao | 2014-03-18 |
| 8630132 | SRAM read and write assist apparatus | Chung-Cheng Chou, Jonathan Tsung-Yung Chang | 2014-01-14 |
| 8437215 | Memory with word-line segment access | Hsiu-Feng Peng, Ming-Zhang Kuo, Chung-Cheng Chou | 2013-05-07 |
| 8437166 | Word line driver cell layout for SRAM and other semiconductor devices | Shu-Cheng Huang, Hsin-Hsin Ko, Jung-Hsuan Chen | 2013-05-07 |