Issued Patents All Time
Showing 26–50 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10951200 | Clock circuit and method of operating the same | Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Fu-An Wu, Yangsyu Lin | 2021-03-16 |
| 10878855 | Low cell voltage (LCV) memory write assist | Yangsyu Lin, Wei-jer Hsieh | 2020-12-29 |
| 10872659 | Memory system having write assist circuit including memory-adapted transistors | Yangsyu Lin, Jonathan Tsung-Yung Chang, Shang-Chi Wu | 2020-12-22 |
| 10867646 | Bit line logic circuits and methods | Shang-Chi Wu, Jonathan Tsung-Yung Chang, Yangsyu Lin, Mahmut Sinangil | 2020-12-15 |
| 10847210 | Memory device with fly word line | Yangsyu Lin | 2020-11-24 |
| 10847217 | Pre-charging bit lines through charge-sharing | Mahmut Sinangil, Hung-Jen Liao, Tsung-Yung Chang | 2020-11-24 |
| 10818677 | Layout of static random access memory periphery circuit | Yangsyu Lin, Chi-Lung Lee, Chien-Chi TIEN | 2020-10-27 |
| 10811085 | Dual rail device with power detector | Yangsyu Lin | 2020-10-20 |
| 10762934 | Leakage pathway prevention in a memory storage device | Shang-Chi Wu, Cheng Hung Lee, Chien-Kuo Su, Yu-Hao Hsu, Yangsyu Lin | 2020-09-01 |
| 10622039 | Dual rail memory with bist circuitry, memory macro and associated hybrid power supply method | Yangsyu Lin | 2020-04-14 |
| 10574213 | Clock circuit and method of operating the same | Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Fu-An Wu, Yangsyu Lin | 2020-02-25 |
| 10559333 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen +2 more | 2020-02-11 |
| 10553275 | Device having write assist circuit including memory-adapted transistors and method for making the same | Yangsyu Lin, Jonathan Tsung-Yung Chang, Shang-Chi Wu | 2020-02-04 |
| 10503421 | Configurable memory storage system | Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Fu-An Wu, Hung-Jen Liao +6 more | 2019-12-10 |
| 10490263 | Dual rail device with power detector | Yangsyu Lin | 2019-11-26 |
| 10410715 | Pre-charging bit lines through charge-sharing | Mahmut Sinangil, Hung-Jen Liao, Tsung-Yung Chang | 2019-09-10 |
| 10340897 | Clock generating circuit and method of operating the same | Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Fu-An Wu, Yangsyu Lin | 2019-07-02 |
| 10319421 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen +2 more | 2019-06-11 |
| 10281502 | Maximum voltage selection circuit | Chia-Chen Kuo, Wei-jer Hsieh | 2019-05-07 |
| 10263621 | Level shifter with improved voltage difference | Shang-Chi Wu, Wei-jer Hsieh, Yangsyu Lin | 2019-04-16 |
| 10163470 | Dual rail memory, memory macro and associated hybrid power supply method | Yangsyu Lin | 2018-12-25 |
| 10141045 | Dual rail device with power detector for controlling power to first and second power domains | Yangsyu Lin | 2018-11-27 |
| 9997219 | Memory macro and method of operating the same | Chien-Kuo Su, Cheng Hung Lee, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen +2 more | 2018-06-12 |
| 9959916 | Dual rail memory, memory macro and associated hybrid power supply method | Jonathan Tsung-Yung Chang, Cheng Hung Lee, Hung-Jen Liao, Michael Patrick Clinton | 2018-05-01 |
| 9922701 | Pre-charging bit lines through charge-sharing | Mahmut Sinangil, Hung-Jen Liao, Tsung-Yung Chang | 2018-03-20 |