Issued Patents All Time
Showing 826–850 of 937 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9899269 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Wai-Yi Lien, Ying-Keung Leung | 2018-02-20 |
| 9899489 | Vertical gate all around (VGAA) devices and methods of manufacturing the same | Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu +1 more | 2018-02-20 |
| 9899519 | Defect-Free SiGe source/drain formation by epitaxy-free process | Shih-Hsieng Huang, Ta-Wei Wang | 2018-02-20 |
| 9887269 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Ching-Fang Huang, Carlos H. Diaz, Wen-Hsing Hsieh, Ying-Keung Leung | 2018-02-06 |
| 9881922 | Semiconductor device and method | Hong-Lin Chen, Shih-Cheng Chen, Ming-Shan Shieh, Chin-Chi Wang, Wai-Yi Lien | 2018-01-30 |
| 9882032 | Structure and method for FinFET device with buried sige oxide | Kuo-Cheng Ching, Zhiqiang Wu, Carlos H. Diaz | 2018-01-30 |
| 9881993 | Method of forming semiconductor structure with horizontal gate all around structure | Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz | 2018-01-30 |
| 9871141 | Thermally tuning strain in semiconductor devices | Carlos H. Diaz, Gwan Sin Chang, Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu | 2018-01-16 |
| 9871111 | Semiconductor device and method | Ming-Ta Hsieh, Tetsu Ohtou, Ching-Wei Tsai | 2018-01-16 |
| 9847425 | FinFET with a semiconductor strip as a base | Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Ying-Keung Leung, Carlos H. Diaz | 2017-12-19 |
| 9818872 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Wai-Yi Lien, Ying-Keung Leung | 2017-11-14 |
| 9773786 | FETs and methods of forming FETs | Kuo-Cheng Ching, Chi-Wen Liu | 2017-09-26 |
| 9764950 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Ta-Pen Guo, Carlos H. Diaz | 2017-09-19 |
| 9755033 | Semiconductor device and method of forming vertical structure | Wai-Yi Lien, Shi Ning Ju, Kai-Chieh Yang, Wen-Ting Lan | 2017-09-05 |
| 9754840 | Horizontal gate-all-around device having wrapped-around source and drain | Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Wen-Hsing Hsieh, Yi-Ming Sheu | 2017-09-05 |
| 9741821 | Two-step dummy gate formation | Kuo-Cheng Ching, Kuan-Ting Pan, Ying-Keung Leung, Carlos H. Diaz | 2017-08-22 |
| 9728505 | Methods and structrues of novel contact feature | Wei-Hao Wu, Chia-Hao Chang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin +2 more | 2017-08-08 |
| 9716096 | Semiconductor structure with feature spacer and method for manufacturing the same | Kuo-Cheng Ching, Chun-Hsiung Lin, Ying-Keung Leung, Carlos H. Diaz | 2017-07-25 |
| 9711413 | High performance CMOS device design | Shang-Chih Chen, Ching-Wei Tsai, Ta-Wei Wang, Pang-Yen Tsai | 2017-07-18 |
| 9711535 | Method of forming FinFET channel | Ching-Wei Tsai, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien | 2017-07-18 |
| 9711533 | FinFET devices having different source/drain proximities for input/output devices and non-input/output devices and the method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Ying-Keung Leung | 2017-07-18 |
| 9711595 | Semiconductor device including a semiconductor sheet unit interconnecting a source and a drain | Jiun-Peng Wu, Tetsu Ohtou, Ching-Wei Tsai, Chi-Wen Liu | 2017-07-18 |
| 9704883 | FETS and methods of forming FETS | Ching-Wei Tsai, Chi-Wen Liu, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien | 2017-07-11 |
| 9698261 | Vertical device architecture | Jhon Jhy Liaw, Wai-Yi Lien, Jia-Chuan You, Yi-Hsun Chiu, Ching-Wei Tsai +1 more | 2017-07-04 |
| 9698242 | Semiconductor arrangement and formation thereof | Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Jiun-Peng Wu | 2017-07-04 |