Issued Patents All Time
Showing 76–100 of 129 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10446406 | High-density semiconductor device | Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Chin-Yuan Tseng, Hsin-Chih Chen +6 more | 2019-10-15 |
| 10388644 | Method of manufacturing conductors and semiconductor device which includes conductors | Kam-Tou Sio, Chih-Liang Chen, Chih-Ming Lai, Hui-Ting Yang, Ko-Bin Kao +2 more | 2019-08-20 |
| 10366200 | System for and method of manufacturing a layout design of an integrated circuit | Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Kam-Tou Sio +3 more | 2019-07-30 |
| 10345304 | Multifunctional nanoprobe-enabled capture and early detection of microbial pathogens | Chao Wang, Kellogg Schwab | 2019-07-09 |
| 10297588 | Semiconductor device and fabrication method of the same | Wei-Cheng Lin, Hui-Ting Yang, Shih-Wei Peng, Jiann-Tyng Tzeng, Chih-Ming Lai | 2019-05-21 |
| 10282197 | Open application lifecycle management framework | Shashi Velur, Raymond Chase, Randal Lee Guck, Ernst Ambichl, Ronald D. Sauers +1 more | 2019-05-07 |
| 10276499 | Dual power structure with connection pins | Shih-Wei Peng, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Jiann-Tyng Tzeng +3 more | 2019-04-30 |
| 10204857 | Middle end-of-line strap for standard cell | Meng-Hung Shen, Chih-Liang Chen, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin | 2019-02-12 |
| 10177133 | Semiconductor device including source/drain contact having height below gate stack | Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun Li Chen, Kam-Tou Sio +3 more | 2019-01-08 |
| 10170422 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Chi-Yeh Yu, Jiann-Tyng Tzeng, Kam-Tou Sio +6 more | 2019-01-01 |
| 10157922 | Interconnect metal layout for integrated circuit | Wei-Cheng Lin, Kam-Tou Sio, Jiann-Tyng Tzeng | 2018-12-18 |
| 10109582 | Advanced metal connection with metal cut | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Hui-Ting Yang +6 more | 2018-10-23 |
| 10096522 | Dummy MOL removal for performance enhancement | Hui-Ting Yang, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Jiann-Tyng Tzeng +4 more | 2018-10-09 |
| 10074657 | Method of manufacturing fins and semiconductor device which includes fins | Chih-Liang Chen, Chih-Ming Lai, Chin-Yuan Tseng, Jiann-Tyng Tzeng, Kam-Tou Sio +3 more | 2018-09-11 |
| 10050028 | Semiconductor device with reduced leakage current | Shih-Wei Peng, Chung-Hsing Wang, Chih-Liang Chen, Jiann-Tyng Tzeng, Yi-Hsun Chiu +1 more | 2018-08-14 |
| 10032759 | High-density semiconductor device | Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu +2 more | 2018-07-24 |
| 9984964 | Integrated circuit having slot via and method of forming the same | Wei-Cheng Lin, Jiann-Tyng Tzeng, Praneeth Narayanasetti | 2018-05-29 |
| 9917050 | Semiconductor device including source/drain contact having height below gate stack | Chih-Liang Chen, Chih-Ming Lai, Kam-Tou Sio, Ru-Gun Liu, Meng-Hung Shen +2 more | 2018-03-13 |
| 9911697 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Chi-Yeh Yu, Jiann-Tyng Tzeng, Kam-Tou Sio +6 more | 2018-03-06 |
| 9837353 | Middle end-of-line strap for standard cell | Meng-Hung Shen, Chih-Liang Chen, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin | 2017-12-05 |
| 9793211 | Dual power structure with connection pins | Shih-Wei Peng, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Jiann-Tyng Tzeng +3 more | 2017-10-17 |
| 9754881 | Designed-based interconnect structure in semiconductor structure | Chih-Liang Chen, Chih-Ming Lai, Yung-Sung Yen, Kam-Tou Sio, Tsong-Hua Ou +3 more | 2017-09-05 |
| 9741654 | Integrated circuit having slot via and method of forming the same | Wei-Cheng Lin, Jiann-Tyng Tzeng, Praneeth Narayanasetti | 2017-08-22 |
| 9679994 | High fin cut fabrication process | L. C. Chou, Chih-Liang Chen, Chih-Ming Lai, Chin-Yuan Tseng, Jiann-Tyng Tzeng +3 more | 2017-06-13 |
| 9659115 | Thermal analysis for tiered semiconductor structure | Chih-Liang Chen, Jiann-Tyng Tzeng, Shu-Hui Sung | 2017-05-23 |