Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7774663 | Dynamically reconfigurable shared scan-in test architecture | Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala +1 more | 2010-08-10 |
| 7743299 | Dynamically reconfigurable shared scan-in test architecture | Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala +1 more | 2010-06-22 |
| 7669098 | Method and apparatus for limiting power dissipation in test | Thomas W. Williams | 2010-02-23 |
| 7596733 | Dynamically reconfigurable shared scan-in test architecture | Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala +1 more | 2009-09-29 |
| 7546500 | Slack-based transition-fault testing | Tom W. Williams, Cyrus Hay | 2009-06-09 |
| 7418640 | Dynamically reconfigurable shared scan-in test architecture | Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala +1 more | 2008-08-26 |
| 6993694 | Deterministic bist architecture including MISR filter | Thomas W. Williams, Tony Taylor, Peter Wohl, John A. Waicukauski | 2006-01-31 |
| 6990619 | System and method for automatically retargeting test vectors between different tester types | Thomas W. Williams | 2006-01-24 |
| 6807646 | System and method for time slicing deterministic patterns for reseeding in logic built-in self-test | Thomas W. Williams, Peter Wohl, John A. Waicukauski | 2004-10-19 |
| 6766501 | System and method for high-level test planning for layout | Suryanarayana Duggirala, Thomas W. Williams | 2004-07-20 |
| 6631344 | Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation | Thomas W. Williams | 2003-10-07 |
| 6615380 | Dynamic scan chains and test pattern generation methodologies therefor | Denis Martin, Thomas W. Williams | 2003-09-02 |
| 6453437 | Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation | Thomas W. Williams, John A. Waicukauski, Peter Wohl | 2002-09-17 |
| 6434733 | System and method for high-level test planning for layout | Suryanarayana Duggirala, Thomas W. Williams | 2002-08-13 |
| 6405355 | Method for placement-based scan-in and scan-out ports selection | Suryanarayana Duggirala, Thomas W. Williams | 2002-06-11 |
| 6385750 | Method and system for controlling test data volume in deterministic test pattern generation | Thomas W. Williams, John A. Waicukauski, Peter Wohl | 2002-05-07 |
| 5691990 | Hybrid partial scan method | Thomas J. Snethen, Kamran Zarrineh | 1997-11-25 |