| 7072239 |
Method and circuit for locating anomalous memory cells |
Rosario Portoghese, Massimo Andreasi Bassi, Stefano Scuratti |
2006-07-04 |
|
| 6677206 |
Non-volatile high-performance memory device and relative manufacturing process |
Federico Pio |
2004-01-13 |
$14,350,000 |
| 6624015 |
Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions |
Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana |
2003-09-23 |
$14,097,000 |
| 6614080 |
Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication |
Bruno Vajana |
2003-09-02 |
$24,157,000 |
| 6576517 |
Method for obtaining a multi-level ROM in an EEPROM process flow |
Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana |
2003-06-10 |
$27,883,000 |
| 6573130 |
Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors |
Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana |
2003-06-03 |
$40,024,000 |
| 6551892 |
Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure therefor |
Federico Pio |
2003-04-22 |
$13,410,000 |
| 6528885 |
Anti-deciphering contacts |
Bruno Vajana |
2003-03-04 |
$19,425,000 |
| 6521957 |
Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell |
Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana |
2003-02-18 |
$17,603,000 |
| 6501147 |
Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained |
Bruno Vajana |
2002-12-31 |
$17,859,000 |
| 6444526 |
Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells |
Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana |
2002-09-03 |
$29,813,000 |
| 6420769 |
Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions |
Nadia Galbiati, Giovanna Dalla Libera, Bruno Vajana |
2002-07-16 |
$15,489,000 |
| 6414349 |
High efficiency memory device |
Giovanna Dalla Libera, Bruno Vajana, Nadia Galbiati |
2002-07-02 |
$16,984,000 |
| 6396101 |
Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions |
Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana |
2002-05-28 |
$26,032,000 |
| 6351008 |
Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions |
Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana |
2002-02-26 |
$19,973,000 |
| 6350652 |
Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions |
Giovanna Dalla Libera, Bruno Vajana |
2002-02-26 |
$19,973,000 |
| 6340828 |
Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions |
Giovanna Dalla Libera, Bruno Vajana |
2002-01-22 |
$161,665,000 |
| 6300181 |
Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistors |
Nadia Galbiati, Giovanna Dalla Libera, Bruno Vajana |
2001-10-09 |
$21,821,000 |
| 6284607 |
Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide |
Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana |
2001-09-04 |
$28,496,000 |
| 6281077 |
Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions |
Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana |
2001-08-28 |
$34,884,000 |
| 6278159 |
Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure therefor |
Federico Pio |
2001-08-21 |
$44,320,000 |
| 6274411 |
Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks |
Bruno Vajana, Giovanna Dalla Libera, Carlo Cremonesi, Nadia Galbiati |
2001-08-14 |
$39,544,000 |
| 6251728 |
Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions |
Nadia Galbiati, Giovanna Dalla Libera, Bruno Vajana |
2001-06-26 |
$22,689,000 |
| 6240011 |
Eeprom cell with improved current performance |
Giovanna Dalla Libera |
2001-05-29 |
$34,457,000 |
| 6177313 |
Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell |
Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana |
2001-01-23 |
$76,756,000 |