Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7072239 | Method and circuit for locating anomalous memory cells | Rosario Portoghese, Massimo Andreasi Bassi, Stefano Scuratti | 2006-07-04 |
| 6677206 | Non-volatile high-performance memory device and relative manufacturing process | Federico Pio | 2004-01-13 |
| 6624015 | Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions | Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana | 2003-09-23 |
| 6614080 | Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication | Bruno Vajana | 2003-09-02 |
| 6576517 | Method for obtaining a multi-level ROM in an EEPROM process flow | Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana | 2003-06-10 |
| 6573130 | Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors | Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana | 2003-06-03 |
| 6551892 | Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure therefor | Federico Pio | 2003-04-22 |
| 6528885 | Anti-deciphering contacts | Bruno Vajana | 2003-03-04 |
| 6521957 | Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell | Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana | 2003-02-18 |
| 6501147 | Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained | Bruno Vajana | 2002-12-31 |
| 6444526 | Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells | Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana | 2002-09-03 |
| 6420769 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions | Nadia Galbiati, Giovanna Dalla Libera, Bruno Vajana | 2002-07-16 |
| 6414349 | High efficiency memory device | Giovanna Dalla Libera, Bruno Vajana, Nadia Galbiati | 2002-07-02 |
| 6396101 | Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions | Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana | 2002-05-28 |
| 6351008 | Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions | Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana | 2002-02-26 |
| 6350652 | Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions | Giovanna Dalla Libera, Bruno Vajana | 2002-02-26 |
| 6340828 | Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions | Giovanna Dalla Libera, Bruno Vajana | 2002-01-22 |
| 6300181 | Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistors | Nadia Galbiati, Giovanna Dalla Libera, Bruno Vajana | 2001-10-09 |
| 6284607 | Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide | Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana | 2001-09-04 |
| 6281077 | Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions | Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana | 2001-08-28 |
| 6278159 | Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure therefor | Federico Pio | 2001-08-21 |
| 6274411 | Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks | Bruno Vajana, Giovanna Dalla Libera, Carlo Cremonesi, Nadia Galbiati | 2001-08-14 |
| 6251728 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions | Nadia Galbiati, Giovanna Dalla Libera, Bruno Vajana | 2001-06-26 |
| 6240011 | Eeprom cell with improved current performance | Giovanna Dalla Libera | 2001-05-29 |
| 6177313 | Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell | Giovanna Dalla Libera, Nadia Galbiati, Bruno Vajana | 2001-01-23 |