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Nadia Galbiati

SS Stmicroelectronics Sa: 15 patents #236 of 4,662Top 6%
Overall (All Time): #327,596 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6624015 Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2003-09-23
6576517 Method for obtaining a multi-level ROM in an EEPROM process flow Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2003-06-10
6573130 Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2003-06-03
6521957 Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2003-02-18
6444526 Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2002-09-03
6420769 Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2002-07-16
6414349 High efficiency memory device Giovanna Dalla Libera, Matteo Patelmo, Bruno Vajana 2002-07-02
6396101 Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2002-05-28
6351008 Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2002-02-26
6300181 Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistors Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2001-10-09
6284607 Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2001-09-04
6281077 Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2001-08-28
6274411 Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks Matteo Patelmo, Bruno Vajana, Giovanna Dalla Libera, Carlo Cremonesi 2001-08-14
6251728 Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2001-06-26
6177313 Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell Matteo Patelmo, Giovanna Dalla Libera, Bruno Vajana 2001-01-23