Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6624015 | Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2003-09-23 |
| 6576517 | Method for obtaining a multi-level ROM in an EEPROM process flow | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2003-06-10 |
| 6573130 | Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2003-06-03 |
| 6548857 | Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process | Bruno Vajana | 2003-04-15 |
| 6521957 | Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2003-02-18 |
| 6479347 | Simplified DSCP process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells | Bruno Vajana | 2002-11-12 |
| 6444526 | Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2002-09-03 |
| 6432762 | Memory cell for EEPROM devices, and corresponding fabricating process | Bruno Vajana, Roberta Bottini, Carlo Cremonesi | 2002-08-13 |
| 6320219 | Memory cell for EEPROM devices and corresponding fabricating process | Bruno Vajana, Carlo Cremonesi, Roberta Bottini | 2001-11-20 |
| 6300181 | Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistors | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2001-10-09 |
| 6284607 | Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2001-09-04 |
| 6268247 | Memory cell of the EEPROM type having its threshold set by implantation, and fabrication method | Carlo Cremonesi, Bruno Vajana, Roberta Bottini | 2001-07-31 |
| 6204531 | Non-volatile memory structure and corresponding manufacturing process | Federico Pio | 2001-03-20 |
| 6194270 | Process for the manufacturing of an electrically programmable non-volatile memory device | Roberta Bottini, Bruno Vajana, Carlo Cremonesi | 2001-02-27 |
| 6177313 | Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2001-01-23 |
| 6097057 | Memory cell for EEPROM devices, and corresponding fabricating process | Bruno Vajana, Roberta Bottini, Carlo Cremonesi | 2000-08-01 |
| 6080626 | Memory cell for EEPROM devices, and corresponding fabricating process | Bruno Vajana, Carlo Cremonesi, Roberta Bottini | 2000-06-27 |
| 5985718 | Process for fabricating memory cells with two levels of polysilicon for devices of EEPROM type | Bruno Vajana, Roberta Bottini, Carlo Cremonesi | 1999-11-16 |