Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6624015 | Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions | Matteo Patelmo, Giovanna Dalla Libera, Nadia Galbiati | 2003-09-23 |
| 6614080 | Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication | Matteo Patelmo | 2003-09-02 |
| 6576517 | Method for obtaining a multi-level ROM in an EEPROM process flow | Matteo Patelmo, Giovanna Dalla Libera, Nadia Galbiati | 2003-06-10 |
| 6573130 | Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors | Matteo Patelmo, Giovanna Dalla Libera, Nadia Galbiati | 2003-06-03 |
| 6548857 | Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process | Giovanna Dalla Libera | 2003-04-15 |
| 6548354 | Process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information | Roberta Bottini, Giovanna Dalla Libera, Federico Pio | 2003-04-15 |
| 6528885 | Anti-deciphering contacts | Matteo Patelmo | 2003-03-04 |
| 6521957 | Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell | Matteo Patelmo, Giovanna Dalla Libera, Nadia Galbiati | 2003-02-18 |
| 6501147 | Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained | Matteo Patelmo | 2002-12-31 |
| 6479347 | Simplified DSCP process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells | Giovanna Dalla Libera | 2002-11-12 |
| 6444526 | Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells | Matteo Patelmo, Giovanna Dalla Libera, Nadia Galbiati | 2002-09-03 |
| 6437395 | Process for the manufacturing of an electrically programmable non-volatile memory device | Roberta Bottini, Giovanna Dalla Libera, Carlo Cremonesi | 2002-08-20 |
| 6432762 | Memory cell for EEPROM devices, and corresponding fabricating process | Giovanna Dalla Libera, Roberta Bottini, Carlo Cremonesi | 2002-08-13 |
| 6420769 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions | Matteo Patelmo, Nadia Galbiati, Giovanna Dalla Libera | 2002-07-16 |
| 6414349 | High efficiency memory device | Giovanna Dalla Libera, Matteo Patelmo, Nadia Galbiati | 2002-07-02 |
| 6396101 | Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions | Matteo Patelmo, Giovanna Dalla Libera, Nadia Galbiati | 2002-05-28 |
| 6380034 | Process for manufacturing memory cells with dimensional control of the floating gate regions | Giovanna Dalla Libera | 2002-04-30 |
| 6350652 | Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions | Giovanna Dalla Libera, Matteo Patelmo | 2002-02-26 |
| 6351008 | Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions | Matteo Patelmo, Giovanna Dalla Libera, Nadia Galbiati | 2002-02-26 |
| 6340828 | Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions | Giovanna Dalla Libera, Matteo Patelmo | 2002-01-22 |
| 6329254 | Memory cell of the EEPROM type having its threshold adjusted by implantation, and fabrication method | Carlo Cremonesi, Roberta Bottini, Giovanna Dalla Libera | 2001-12-11 |
| 6320219 | Memory cell for EEPROM devices and corresponding fabricating process | Carlo Cremonesi, Roberta Bottini, Giovanna Dalla Libera | 2001-11-20 |
| 6307229 | Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips | Nicola Zatelli, Federico Pio | 2001-10-23 |
| 6300181 | Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistors | Matteo Patelmo, Nadia Galbiati, Giovanna Dalla Libera | 2001-10-09 |
| 6284607 | Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide | Matteo Patelmo, Giovanna Dalla Libera, Nadia Galbiati | 2001-09-04 |