Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6281077 | Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions | Matteo Patelmo, Giovanna Dalla Libera, Nadia Galbiati | 2001-08-28 |
| 6274411 | Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks | Matteo Patelmo, Giovanna Dalla Libera, Carlo Cremonesi, Nadia Galbiati | 2001-08-14 |
| 6268247 | Memory cell of the EEPROM type having its threshold set by implantation, and fabrication method | Carlo Cremonesi, Roberta Bottini, Giovanna Dalla Libera | 2001-07-31 |
| 6251728 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions | Matteo Patelmo, Nadia Galbiati, Giovanna Dalla Libera | 2001-06-26 |
| 6221717 | EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process | Carlo Cremonesi, Roberta Bottini, Giovanna Dalla Libera | 2001-04-24 |
| 6194270 | Process for the manufacturing of an electrically programmable non-volatile memory device | Roberta Bottini, Giovanna Dalla Libera, Carlo Cremonesi | 2001-02-27 |
| 6177313 | Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell | Matteo Patelmo, Giovanna Dalla Libera, Nadia Galbiati | 2001-01-23 |
| 6144588 | Monolithically integrated generator of a plurality of voltage values | Federico Pio, Paola Paruzzi | 2000-11-07 |
| 6097057 | Memory cell for EEPROM devices, and corresponding fabricating process | Giovanna Dalla Libera, Roberta Bottini, Carlo Cremonesi | 2000-08-01 |
| 6080626 | Memory cell for EEPROM devices, and corresponding fabricating process | Carlo Cremonesi, Roberta Bottini, Giovanna Dalla Libera | 2000-06-27 |
| 5985718 | Process for fabricating memory cells with two levels of polysilicon for devices of EEPROM type | Giovanna Dalla Libera, Roberta Bottini, Carlo Cremonesi | 1999-11-16 |
| 5850360 | High-voltage N-channel MOS transistor and associated manufacturing process | Livio Baldi | 1998-12-15 |
| 5793085 | Bipolar transistor compatible with CMOS processes | Emilio Ghio | 1998-08-11 |
| 5732012 | Rom cell with reduced drain capacitance | Paolo Cappelletti, Silvia Lucherini | 1998-03-24 |
| 5486487 | Method for adjusting the threshold of a read-only memory to achieve low capacitance and high breakdown voltage | Giancarlo Ginami, Enrico Laurin, Silvia Lucherini | 1996-01-23 |
| 5328863 | Process for manufacturing a ROM cell with low drain capacitance | Paolo Cappelletti, Silvia Lucherini | 1994-07-12 |
| 5322803 | Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells | Paolo Cappelletti, Giuseppe Corda, Paolo Ghezzi, Carlo Riva | 1994-06-21 |