Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE37308 | EEPROM memory cell with a single level of polysilicon programmable and erasable bit by bit | Paolo Cappelletti, Carlo Riva | 2001-08-07 |
| 5322803 | Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells | Paolo Cappelletti, Paolo Ghezzi, Carlo Riva, Bruno Vajana | 1994-06-21 |
| 5081057 | Electrically alterable, nonvolatile, floating gate type memory device with reduced tunnelling area and fabrication thereof | — | 1992-01-14 |
| 4935790 | EEPROM memory cell with a single level of polysilicon programmable and erasable bit by bit | Paolo Cappelletti, Carlo Riva | 1990-06-19 |
| 4931847 | Floating gate memory with sidewall tunnelling area | — | 1990-06-05 |
| 4896295 | Eprom memory cell with two symmetrical half-cells and separate floating gates | — | 1990-01-23 |
| 4792925 | Eprom memory matrix with symmetrical elementary MOS cells and writing method therefor | Andrea Ravaglia | 1988-12-20 |
| 4703552 | Fabricating a CMOS transistor having low threshold voltages using self-aligned silicide polysilicon gates and silicide interconnect regions | Livio Baldi, Giulio Iannuzzi, Danilo Re, Giorgio De Santi | 1987-11-03 |
| 4412311 | Storage cell for nonvolatile electrically alterable memory | Franco Miccoli | 1983-10-25 |
| 4357685 | Method of programming an electrically alterable nonvolatile memory | Vincenzo Daniele, Aldo Magrucci, Guido Torelli | 1982-11-02 |
| 4315239 | Process for producing a calibrated resistance element and integrated circuitry incorporating same | Vincenzo Daniele, Andrea Ravaglia, Giuseppe Ferla | 1982-02-09 |
| 4310571 | Process for producing a calibrated resistance element | Vincenzo Daniele, Andrea Ravaglia, Giuseppe Ferla | 1982-01-12 |