Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6642582 | Circuit structure with a parasitic transistor having high threshold voltage | Federico Pio | 2003-11-04 |
| 6548354 | Process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information | Roberta Bottini, Bruno Vajana, Federico Pio | 2003-04-15 |
| 6437395 | Process for the manufacturing of an electrically programmable non-volatile memory device | Roberta Bottini, Bruno Vajana, Carlo Cremonesi | 2002-08-20 |
| 6420769 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2002-07-16 |
| 6414349 | High efficiency memory device | Matteo Patelmo, Bruno Vajana, Nadia Galbiati | 2002-07-02 |
| 6396101 | Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2002-05-28 |
| 6380034 | Process for manufacturing memory cells with dimensional control of the floating gate regions | Bruno Vajana | 2002-04-30 |
| 6351008 | Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2002-02-26 |
| 6350652 | Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions | Bruno Vajana, Matteo Patelmo | 2002-02-26 |
| 6340828 | Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions | Bruno Vajana, Matteo Patelmo | 2002-01-22 |
| 6329254 | Memory cell of the EEPROM type having its threshold adjusted by implantation, and fabrication method | Carlo Cremonesi, Bruno Vajana, Roberta Bottini | 2001-12-11 |
| 6281077 | Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2001-08-28 |
| 6274411 | Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks | Matteo Patelmo, Bruno Vajana, Carlo Cremonesi, Nadia Galbiati | 2001-08-14 |
| 6251728 | Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2001-06-26 |
| 6240011 | Eeprom cell with improved current performance | Matteo Patelmo | 2001-05-29 |
| 6221717 | EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process | Carlo Cremonesi, Bruno Vajana, Roberta Bottini | 2001-04-24 |