| 7685470 |
Method and device for debugging a program executed by a multitask processor |
Renaud Ayrignac, Isabelle Sename |
2010-03-23 |
$6,387,000 |
| 7496737 |
High priority guard transfer for execution control of dependent guarded instructions |
Laurent Uguen, Sebastien Ferroussat, Thomas Alofs |
2009-02-24 |
$1,957,000 |
| 7486582 |
Dynamic memory for a cellular terminal |
Francois Druilhe, Denis DUTOIT, Michel Harrand, Gilles Eyzat, Christian Freund |
2009-02-03 |
$3,173,000 |
| 7441109 |
Computer system with a debug facility for a pipelined processor using predicated execution |
Laurent Wojcieszak, Isabelle Sename |
2008-10-21 |
$6,125,000 |
| 7370182 |
Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor |
Anne Merlande, Sebastien Ferroussat |
2008-05-06 |
$3,132,000 |
| 7290089 |
Executing cache instructions in an increased latency mode |
Sivagnanam Parthasarathy, Lionel Chaverot |
2007-10-30 |
$3,992,000 |
| 7281119 |
Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modes |
Bruno Fel, Laurent Ducousso |
2007-10-09 |
$3,290,000 |
| 7240185 |
Computer system with two debug watch modes for controlling execution of guarded instructions upon breakpoint detection |
Laurent Wojcieszak, Isabelle Sename |
2007-07-03 |
$6,904,000 |
| 7111152 |
Computer system that operates in VLIW and superscalar modes and has selectable dependency control |
Bruno Fel, Laurent Ducousso |
2006-09-19 |
$5,111,000 |
| 7013256 |
Computer system with debug facility |
Laurent Wojcieszak, Arnaud Dehamel, Isabelle Sename |
2006-03-14 |
$8,752,000 |
| 6959379 |
Multiple execution of instruction loops within a processor without accessing program memory |
Laurent Wojcieszak |
2005-10-25 |
$9,407,000 |
| 6889313 |
Selection of decoder output from two different length instruction decoders |
Stéphane Bouvier, Laurent Wojcieszak |
2005-05-03 |
$4,788,000 |
| 6854049 |
Method of handling instructions within a processor with decoupled architecture, in particular a processor for digital signal processing, and corresponding processor |
— |
2005-02-08 |
$6,459,000 |
| 6807626 |
Execution of a computer program |
Stéphane Bouvier, Bruno Fel, Laurent Ducousso |
2004-10-19 |
$8,675,000 |
| 6754856 |
Memory access debug facility |
Isabelle Sename, Bruno Bernard |
2004-06-22 |
$11,676,000 |
| 6742131 |
Instruction supply mechanism |
Laurent Wojcieszak |
2004-05-25 |
$16,091,000 |
| 6732276 |
Guarded computer instruction execution |
Bruno Fel, Laurent Ducousso |
2004-05-04 |
$9,538,000 |
| 6725365 |
Branching in a computer system |
Stéphane Bouvier |
2004-04-20 |
$12,916,000 |
| 6711668 |
Prefetch unit |
Laurent Wojcieszak |
2004-03-23 |
$35,307,000 |
| 6678818 |
Decoding next instruction of different length without length mode indicator change upon length change instruction detection |
Stéphane Bouvier, Laurent Wojcieszak |
2004-01-13 |
$14,350,000 |
| 5848109 |
Apparatus and process for sampling a serial digital signal |
Roland Marbot, Jean-Claude Le Bihan, Anne Pierre Duplessix, Pascal Couteaux, Reza Nezamzadeh-Moosavi |
1998-12-08 |
|
| 5614841 |
Frequency multiplier using XOR/NXOR gates which have equal propagation delays |
Roland Marbot, Jean-Claude Le Bihan, Reza Nezamzadeh-Moosavi |
1997-03-25 |
|
| 5596285 |
Impedance adaptation process and device for a transmitter and/or receiver, integrated circuit and transmission system |
Roland Marbot, Jean-Claude Le Bihan, Reza Nezamzadeh-Moosavi |
1997-01-21 |
|
| 5327031 |
Variable-delay circuit |
Roland Marbot, Michel Combes, Jean-Claude Lebihan, Reza Nezamzadeh-Moosavi |
1994-07-05 |
|