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Lionel Chaverot

SS Stmicroelectronics Sa: 2 patents #2,729 of 4,662Top 60%
Overall (All Time): #3,399,845 of 4,157,543Top 85%
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Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7290089 Executing cache instructions in an increased latency mode Sivagnanam Parthasarathy, Andrew Cofler 2007-10-30