Issued Patents All Time
Showing 51–75 of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7915164 | Method for forming doped polysilicon via connecting polysilicon layers | Michael Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Tanmay Kumar | 2011-03-29 |
| 7915163 | Method for forming doped polysilicon via connecting polysilicon layers | Michael Konevecki, Usha Raghuram, Maitreyee Mahajani, Sucheta Nallamothu, Tanmay Kumar | 2011-03-29 |
| 7855862 | Electrostatic discharge (ESD) circuit and method that includes P-channel device in signal path | Kevin J. Gallagher, Gerald Murphy | 2010-12-21 |
| 7838937 | Circuits providing ESD protection to high voltage laterally diffused metal oxide semiconductor (LDMOS) transistors | Helmut Puchner, Harold Kutz, James H. Shutt | 2010-11-23 |
| 7777268 | Dual-gate device | — | 2010-08-17 |
| 7777269 | Dual-gate device | — | 2010-08-17 |
| 7667241 | Electrostatic discharge protection device | Helmut Puchner | 2010-02-23 |
| 7659558 | Silicon controlled rectifier electrostatic discharge clamp for a high voltage laterally diffused MOS transistor | Helmut Puchner | 2010-02-09 |
| 7638836 | Nonvolatile memory with backplate | — | 2009-12-29 |
| 7615436 | Two mask floating gate EEPROM and method of making | Igor G. Kouznetsov | 2009-11-10 |
| 7612411 | Dual-gate device and method | — | 2009-11-03 |
| 7573695 | Snapdown prevention in voltage controlled MEMS devices | Marc D. Hartranft, Michael J. Duewake, Gerald Murphy, Kevin J. Gallagher | 2009-08-11 |
| 7566974 | Doped polysilicon via connecting polysilicon layers | Michael Konevecki, Usha Raghuram, Maitreyee Mahajani, Tanmay Kumar, Sucheta Nallamothu | 2009-07-28 |
| 7529017 | Circuit and method for snapdown prevention in voltage controlled MEMS devices | Marc D. Hartranft, Michael Dueweke | 2009-05-05 |
| 7525137 | TFT mask ROM and method for making same | Christopher J. Petti | 2009-04-28 |
| 7508714 | Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block | Luca Fasoli, Roy E. Scheuerlein, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani | 2009-03-24 |
| 7505321 | Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same | Roy E. Scheuerlein, Christopher J. Petti, En-Hsing Chen, Sucheta Nallamothu, Alper Ilkbahar +2 more | 2009-03-17 |
| 7495337 | Dual-gate device and method | Maitreyee Mahajani | 2009-02-24 |
| 7462521 | Dual-gate device and method | Maitreyee Mahajani | 2008-12-09 |
| 7459755 | Dual-gate semiconductor devices with enhanced scalability | — | 2008-12-02 |
| 7433233 | NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same | En-Hsing Chen, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli | 2008-10-07 |
| 7410845 | Dual-gate device and method | — | 2008-08-12 |
| 7339821 | Dual-gate nonvolatile memory and method of program inhibition | — | 2008-03-04 |
| 7250646 | TFT mask ROM and method for making same | Christopher J. Petti | 2007-07-31 |
| 7233522 | NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same | En-Hsing Chen, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar, Luca Fasoli | 2007-06-19 |