Issued Patents All Time
Showing 51–67 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9058130 | Tunable sector buffer for wide bandwidth resonant global clock distribution | Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong-im Kim +3 more | 2015-06-16 |
| 9054682 | Wide bandwidth resonant global clock distribution | Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong-im Kim +3 more | 2015-06-09 |
| 8969104 | Circuit technique to electrically characterize block mask shifts | Emrah Acar, Aditya Bansal, Dureseti Chidambarrao, Amith Singhee | 2015-03-03 |
| 8928350 | Programming the behavior of individual chips or strata in a 3D stack of integrated circuits | Joel A. Silberman, Matthew R. Wordeman | 2015-01-06 |
| 8860425 | Defect detection on characteristically capacitive circuit nodes | William Robert Reohr, Phillip J. Restle | 2014-10-14 |
| 8736342 | Changing resonant clock modes | Thomas J. Bucelot, Alan J. Drake, Joshua D. Friedrich, Jason D. Hibbeler, William Robert Reohr +3 more | 2014-05-27 |
| 8704576 | Variable resistance switch for wide bandwidth resonant global clock distribution | Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong-im Kim +3 more | 2014-04-22 |
| 8587357 | AC supply noise reduction in a 3D stack with voltage sensing and clock shifting | Jae-Joon Kim, Yu-Shiang Lin, Joel A. Silberman | 2013-11-19 |
| 8576000 | 3D chip stack skew reduction with resonant clock and inductive coupling | Jae-Joon Kim, Yu-Shiang Lin, Joel A. Silberman | 2013-11-05 |
| 8525569 | Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network | Thomas J. Bucelot, Phillip J. Restle | 2013-09-03 |
| 8519735 | Programming the behavior of individual chips or strata in a 3D stack of integrated circuits | Joel A. Silberman, Matthew R. Wordeman | 2013-08-27 |
| 8466739 | 3D chip stack skew reduction with resonant clock and inductive coupling | Jae-Joon Kim, Yu-Shiang Lin, Joel A. Silberman | 2013-06-18 |
| 7864625 | Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator | Gary Dale Carpenter, Jente B. Kuang, Kevin John Nowka | 2011-01-04 |
| 7760565 | Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance | Jente B. Kuang, Jerry Chang Jui Kao, Hung C. Ngo, Kevin John Nowka, Jayakumaran Sivagnaname | 2010-07-20 |
| 7668037 | Storage array including a local clock buffer with programmable timing | Gary Dale Carpenter, Fadi H. Gebara, Jerry Chang Jui Kao, Jente B. Kuang, Kevin John Nowka | 2010-02-23 |
| 7620510 | Pulsed ring oscillator circuit for storage cell read timing evaluation | Gary Dale Carpenter, Jente B. Kuang, Kevin John Nowka | 2009-11-17 |
| 7409305 | Pulsed ring oscillator circuit for storage cell read timing evaluation | Gary Dale Carpenter, Jente B. Kuang, Kevin John Nowka | 2008-08-05 |