Issued Patents All Time
Showing 26–50 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9666593 | Alternating refractive index in charge-trapping film in three-dimensional memory | Yingda Dong, Jayavel Pachamuthu | 2017-05-30 |
| 9620233 | Word line ramping down scheme to purge residual electrons | Yingda Dong, Xuehong Yu | 2017-04-11 |
| 9612612 | Tunable sector buffer for wide bandwidth resonant global clock distribution | Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong-im Kim +3 more | 2017-04-04 |
| 9607707 | Weak erase prior to read | Yingda Dong, Xuehong Yu, Jingjian Ren | 2017-03-28 |
| 9595342 | Method and apparatus for refresh programming of memory cells based on amount of threshold voltage downshift | Yingda Dong, Jian Chen | 2017-03-14 |
| 9583198 | Word line-dependent and temperature-dependent pass voltage during programming | Yingda Dong, Jiahui Yuan, Jingjian Ren | 2017-02-28 |
| 9543320 | Three-dimensional memory structure having self-aligned drain regions and methods of making thereof | Jayavel Pachamuthu, Yingda Dong | 2017-01-10 |
| 9490262 | Selective removal of charge-trapping layer for select gate transistor and dummy memory cells in 3D stacked memory | Yingda Dong | 2016-11-08 |
| 9466369 | Word line-dependent ramping of pass voltage and program voltage for three-dimensional memory | Jiahui Yuan, Yingda Dong, Jingjian Ren | 2016-10-11 |
| 9460805 | Word line dependent channel pre-charge for memory | Jiahui Yuan, Yingda Dong | 2016-10-04 |
| 9437305 | Programming memory with reduced short-term charge loss | Ching-Huang Lu, Yingda Dong, Tien-Chien Kuo | 2016-09-06 |
| 9406693 | Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory | Yingda Dong | 2016-08-02 |
| 9406690 | Contact for vertical memory with dopant diffusion stopper and associated fabrication method | Jayavel Pachamuthu, Yingda Dong | 2016-08-02 |
| 9368509 | Three-dimensional memory structure having self-aligned drain regions and methods of making thereof | Jayavel Pachamuthu, Yingda Dong | 2016-06-14 |
| 9349478 | Read with look-back combined with programming with asymmetric boosting in memory | Jiahui Yuan, Yingda Dong, Charles See Yeung Kwong, Hong-Yan Chen | 2016-05-24 |
| 9348357 | Stitchable global clock for 3D chips | Robert L. Franch, Eren Kursun, Phillip J. Restle | 2016-05-24 |
| 9343159 | Avoiding unintentional program or erase of a select gate transistor | Yingda Dong | 2016-05-17 |
| 9343141 | Reprogramming memory with single program pulse per data state | Yingda Dong | 2016-05-17 |
| 9324419 | Multiple pass programming for memory with different program pulse widths | Yingda Dong | 2016-04-26 |
| 9299450 | Adaptive increase in control gate voltage of a dummy memory cell to compensate for inadvertent programming | Yingda Dong, Zhengyi Zhang | 2016-03-29 |
| 9299443 | Modifying program pulses based on inter-pulse period to reduce program noise | Yingda Dong, Jiahui Yuan | 2016-03-29 |
| 9230663 | Programming memory with reduced short-term charge loss | Ching-Huang Lu, Yingda Dong, Tien-Chien Kuo | 2016-01-05 |
| 9231603 | Distributed phase detection for clock synchronization in multi-layer 3D stacks | Yong Liu, Phillip J. Restle | 2016-01-05 |
| 9230676 | Weak erase of a dummy memory cell to counteract inadvertent programming | Yingda Dong, Charles See Yeung Kwong | 2016-01-05 |
| 9165659 | Efficient reprogramming method for tightening a threshold voltage distribution in a memory device | Hong-Yan Chen, Yingda Dong | 2015-10-20 |