Issued Patents All Time
Showing 76–86 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7937556 | Minimizing TLB comparison size | Paul J. Jordan, Gregory F. Grohoski | 2011-05-03 |
| 7747771 | Register access protocol in a multihreaded multi-core processor | Robert T. Golla, Mark Luttrell, Gregory F. Grohoski | 2010-06-29 |
| 7685354 | Multiple-core processor with flexible mapping of processor cores to cache banks | Ricky C. Hetherington, Gregory F. Grohoski, Bikram Saha | 2010-03-23 |
| 7571284 | Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor | Christopher H. Olson | 2009-08-04 |
| 7543132 | Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes | Greg F. Grohoski, Ashley Saulsbury, Paul J. Jordan, Rabin Sugumar, Mark Debbage +1 more | 2009-06-02 |
| 7454590 | Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores | Paul J. Jordan, Gregory F. Grohoski | 2008-11-18 |
| 7434000 | Handling duplicate cache misses in a multithreaded/multi-core processor | Jama I. Barreh | 2008-10-07 |
| 7383415 | Hardware demapping of TLBs shared by multiple threads | Paul J. Jordan, Gregory F. Grohoski | 2008-06-03 |
| 7383403 | Concurrent bypass to instruction buffers in a fine grain multithreaded processor | Jama I. Barreh, Robert T. Golla | 2008-06-03 |
| 7353445 | Cache error handling in a multithreaded/multi-core processor | Jama I. Barreh | 2008-04-01 |
| 7290116 | Level 2 cache index hashing to avoid hot spots | Greg F. Grohoski, John D. Davis, Ashley Saulsbury, Cong Fu, Venkatesh Iyengar +2 more | 2007-10-30 |