Issued Patents All Time
Showing 51–75 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10747540 | Hybrid lookahead branch target cache | Yuan C. Chou | 2020-08-18 |
| 10698853 | Virtualization of a reconfigurable data processor | Gregory F. Grohoski, Sumti Jairath, Mark Luttrell, Raghu Prabhakar, Ram Sivaramakrishnan | 2020-06-30 |
| 10579107 | Reversible connector orientation detection circuitry | James Hao-An Chen Lin, Jyhlin Chang | 2020-03-03 |
| 10474601 | Distributed fairness protocol for interconnect networks | Robert T. Golla, Mark Luttrell | 2019-11-12 |
| 10430342 | Optimizing thread selection at fetch, select, and commit stages of processor core pipeline | Yuan C. Chou, Gideon N. Levinsky, Robert T. Golla, Matthew B. Smittle | 2019-10-01 |
| 10346173 | Multi-threaded instruction buffer design | Jama I. Barreh, Robert T. Golla | 2019-07-09 |
| 10338928 | Utilizing a stack head register with a call return stack for each instruction fetch | Zeid H. Samoail | 2019-07-02 |
| 10318303 | Method and apparatus for augmentation and disambiguation of branch history in pipelined branch predictors | Jared C. Smolens | 2019-06-11 |
| 10255197 | Adaptive tablewalk translation storage buffer predictor | John D. Pape, Gideon N. Levinsky, Jared C. Smolens | 2019-04-09 |
| 10250059 | Charging circuit for battery-powered device | Yazan Aldehayyat, Ricardo Márquez Reyes | 2019-04-02 |
| 10198260 | Processing instruction control transfer instructions | Christopher H. Olson | 2019-02-05 |
| 10001998 | Dynamically enabled branch prediction | Haowei Zhang, Xiaoying Shen | 2018-06-19 |
| 9529594 | Miss buffer for a multi-threaded processor | Jama I. Barreh | 2016-12-27 |
| 9213551 | Return address prediction in multithreaded processors | Gregory F. Grohoski, Zeid H. Samoail | 2015-12-15 |
| 9208261 | Power reduction for fully associated translation lookaside buffer (TLB) and content addressable memory (CAM) | Gideon N. Levinsky | 2015-12-08 |
| 9116876 | Programmable built-in-self tester (BIST) in memory controller | Woo-Tag Kang, Roberto Fabian Averbuj | 2015-08-25 |
| 8904156 | Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor | Gregory F. Grohoski, Robert T. Golla, Jama I. Barreh | 2014-12-02 |
| 8886920 | Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage | Christopher H. Olson | 2014-11-11 |
| 8862861 | Suppressing branch prediction information update by branch instructions in incorrect speculative execution path | Christopher H. Olson | 2014-10-14 |
| 8595464 | Dynamic sizing of translation lookaside buffer for power reduction | Gideon N. Levinsky | 2013-11-26 |
| 8195921 | Method and apparatus for decoding multithreaded instructions of a microprocessor | Robert T. Golla | 2012-06-05 |
| 8195919 | Handling multi-cycle integer operations for a multi-threaded processor | Christopher H. Olson, Robert T. Golla, Jeffrey S. Brooks | 2012-06-05 |
| 8099586 | Branch misprediction recovery mechanism for microprocessors | Yuan C. Chou, Robert T. Golla, Mark Luttrell, Paul J. Jordan | 2012-01-17 |
| 8037250 | Arbitrating cache misses in a multithreaded/multi-core processor | Jama I. Barreh | 2011-10-11 |
| 7996632 | Device for misaligned atomics for a highly-threaded x86 processor | Greg F. Grohoski, Mark Luttrell | 2011-08-09 |