MD

Mark Debbage

IN Intel: 16 patents #2,580 of 30,777Top 9%
HI Hitachi: 3 patents #10,712 of 28,497Top 40%
Oracle: 1 patents #8,282 of 14,854Top 60%
Overall (All Time): #212,560 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12212502 Reliable transport architecture Robert Southworth, Arvind Srinivasan, Cheolmin Park, Todd Rimmer, Brian S. Hausauer 2025-01-28
12190405 Direct memory writes by network interface of a graphics processing unit Todd Rimmer, Bruce Gregory Warren, Sayantan Sur, Nayan Amrutlal Suthar, Ajaya V. Durg 2025-01-07
12177277 System, apparatus, and method for streaming input/output data Lokpraveen Mosur, Ilango S. Ganga, Robert W. Cone, Kshitij A. Doshi, John J. Browne +3 more 2024-12-24
12137001 Scalable protocol-agnostic reliable transport Bruce Gregory Warren 2024-11-05
11467885 Technologies for managing a latency-efficient pipeline through a network interface controller Ronen Aharon Hyatt 2022-10-11
10073796 Sending packets using optimized PIO write sequences without SFENCES Yatin M. Mutha 2018-09-11
10044626 Reliable out-of order end-to-end protocol with robust window state overflow management and a multi-node system using same Keith D. Underwood, Charles A. Giefer, Karl Brummel, Nathan S. Miller, Bruce M. Pirie 2018-08-07
10015056 System, method and apparatus for improving the performance of collective operations in high performance computing Michael Heinz, Todd Rimmer, James A. Kunz 2018-07-03
9984020 Optimized credit return mechanism for packet sends Yatin M. Mutha 2018-05-29
9792235 Optimized credit return mechanism for packet sends Yatin M. Mutha 2017-10-17
9785359 Sending packets using optimized PIO write sequences without sfences and out of order credit returns Yatin M. Mutha 2017-10-10
9734077 Sending packets using optimized PIO write sequences without sfences Yatin M. Mutha 2017-08-15
9588899 Sending packets using optimized PIO write sequences without sfences Yatin M. Mutha 2017-03-07
9477631 Optimized credit return mechanism for packet sends Yatin M. Mutha 2016-10-25
9460019 Sending packets using optimized PIO write sequences without SFENCEs Yatin M. Mutha 2016-10-04
9391845 System, method and apparatus for improving the performance of collective operations in high performance computing Michael Heinz, Todd Rimmer, James A. Kunz 2016-07-12
7543132 Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes Greg F. Grohoski, Ashley Saulsbury, Paul J. Jordan, Manish K. Shah, Rabin Sugumar +1 more 2009-06-02
6591340 Microprocessor having improved memory management unit and cache memory Rajesh Chopra, Shinichi Yoshioka, David Shepherd 2003-07-08
6553460 Microprocessor having improved memory management unit and cache memory Rajesh Chopra, Shinichi Yoshioka 2003-04-22
6412043 Microprocessor having improved memory management unit and cache memory Rajesh Chopra, Shinichi Yoshioka, David Shepherd 2002-06-25