Mark Debbage — 21 Patents at Intel

Mark Debbage has been granted 21 US patents while listed as an inventor at Intel. The first was granted in 2002 and the most recent in October 2025. Mark Debbage ranks #201,324 of 4,157,543 US inventors in our database (top 4.8%). Patent records list Mark Debbage in Santa Clara, CA, US.

Issued Patents All Time

Showing 1–21 of 21 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12438821	System for storage of received messages	—	2025-10-07
12212502	Reliable transport architecture	Robert Southworth, Arvind Srinivasan, Cheolmin Park, Todd Rimmer, Brian S. Hausauer	2025-01-28
12190405	Direct memory writes by network interface of a graphics processing unit	Todd Rimmer, Bruce Gregory Warren, Sayantan Sur, Nayan Amrutlal Suthar, Ajaya V. Durg	2025-01-07
12177277	System, apparatus, and method for streaming input/output data	Lokpraveen Mosur, Ilango S. Ganga, Robert W. Cone, Kshitij A. Doshi, John J. Browne +3 more	2024-12-24	$17,261,000
12137001	Scalable protocol-agnostic reliable transport	Bruce Gregory Warren	2024-11-05	$48,202,000
11467885	Technologies for managing a latency-efficient pipeline through a network interface controller	Ronen Aharon Hyatt	2022-10-11	$16,542,000
10073796	Sending packets using optimized PIO write sequences without SFENCES	Yatin M. Mutha	2018-09-11	$19,778,000
10044626	Reliable out-of order end-to-end protocol with robust window state overflow management and a multi-node system using same	Keith D. Underwood, Charles A. Giefer, Karl Brummel, Nathan S. Miller, Bruce M. Pirie	2018-08-07	$25,284,000
10015056	System, method and apparatus for improving the performance of collective operations in high performance computing	Michael Heinz, Todd Rimmer, James A. Kunz	2018-07-03	$24,450,000
9984020	Optimized credit return mechanism for packet sends	Yatin M. Mutha	2018-05-29	$28,242,000
9792235	Optimized credit return mechanism for packet sends	Yatin M. Mutha	2017-10-17	$9,876,000
9785359	Sending packets using optimized PIO write sequences without sfences and out of order credit returns	Yatin M. Mutha	2017-10-10	$9,084,000
9734077	Sending packets using optimized PIO write sequences without sfences	Yatin M. Mutha	2017-08-15	$8,272,000
9588899	Sending packets using optimized PIO write sequences without sfences	Yatin M. Mutha	2017-03-07	$9,849,000
9477631	Optimized credit return mechanism for packet sends	Yatin M. Mutha	2016-10-25	$11,658,000
9460019	Sending packets using optimized PIO write sequences without SFENCEs	Yatin M. Mutha	2016-10-04	$11,494,000
9391845	System, method and apparatus for improving the performance of collective operations in high performance computing	Michael Heinz, Todd Rimmer, James A. Kunz	2016-07-12	$10,128,000
7543132	Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes	Greg F. Grohoski, Ashley Saulsbury, Paul J. Jordan, Manish K. Shah, Rabin Sugumar +1 more	2009-06-02	$13,808,000
6591340	Microprocessor having improved memory management unit and cache memory	Rajesh Chopra, Shinichi Yoshioka, David Shepherd	2003-07-08	$150,000
6553460	Microprocessor having improved memory management unit and cache memory	Rajesh Chopra, Shinichi Yoshioka	2003-04-22	$117,000
6412043	Microprocessor having improved memory management unit and cache memory	Rajesh Chopra, Shinichi Yoshioka, David Shepherd	2002-06-25	$149,000

Mark Debbage — 21 Patents

Issued Patents All Time

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