Issued Patents All Time
Showing 101–125 of 200 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9824730 | Memory components and controllers that calibrate multiphase synchronous timing references | Thomas J. Giovannini, Lei Luo, Ian Shaeffer | 2017-11-21 |
| 9818470 | Multi-die memory device | Ming Li | 2017-11-14 |
| 9792965 | Memory module and system supporting parallel and serial access modes | Frederick A. Ware, William N. Ng | 2017-10-17 |
| 9741423 | Methods and apparatus for synchronizing communication with a memory controller | Richard E. Warmke, David B. Roberts, Frank Lambrecht | 2017-08-22 |
| 9710011 | Drift tracking feedback for communication channels | Abhijit Abhyankar, Kun-Yung Chang, Frank Lambrecht | 2017-07-18 |
| 9704576 | Complementary RRAM applications for logic and ternary content addressable memory (TCAM) | Brent Haukness | 2017-07-11 |
| 9653146 | High capacity memory system using standard controller component | Frederick A. Ware, Suresh Rajan | 2017-05-16 |
| 9565039 | Forwarding signal supply voltage in data transmission system | John W. Poulton | 2017-02-07 |
| 9490002 | Reduced refresh power | Frederick A. Ware, Brent Haukness, Gary B. Bronner | 2016-11-08 |
| 9479176 | Methods and circuits for protecting integrated circuits from reverse engineering | John Eble, Hanson Quan | 2016-10-25 |
| 9466353 | Methods and apparatus for synchronizing communication with a memory controller | Richard E. Warmke, David B. Roberts, Frank Lambrecht | 2016-10-11 |
| 9450614 | Memory module with integrated error correction | Frederick A. Ware | 2016-09-20 |
| 9412428 | Memory components and controllers that calibrate multiphase synchronous timing references | Thomas J. Giovannini, Lei Luo, Ian Shaeffer | 2016-08-09 |
| 9390782 | Memory with refresh logic to accommodate low-retention storage rows | Ely Tsern | 2016-07-12 |
| 9384152 | Coordinating memory operations using memory-device generated reference signals | Ian Shaeffer | 2016-07-05 |
| 9324411 | Multi-die memory device | Ming Li | 2016-04-26 |
| 9256376 | Methods and circuits for dynamically scaling DRAM power and performance | Ely Tsern, Thomas Vogelsang, Craig E. Hampel | 2016-02-09 |
| 9231731 | Common mode calibration | Huy M. Nguyen, Kambiz Kaviani, Reza Navid, Jason C. Wei, Xudong Shi | 2016-01-05 |
| 9183920 | High capacity memory system using standard controller component | Frederick A. Ware, Suresh Rajan | 2015-11-10 |
| 9171824 | Stacked semiconductor device assembly | — | 2015-10-27 |
| 9165639 | High capacity memory system using standard controller component | Frederick A. Ware, Suresh Rajan | 2015-10-20 |
| 9159388 | Methods and apparatus for synchronizing communication with a memory controller | Richard E. Warmke, David B. Roberts, Frank Lambrecht | 2015-10-13 |
| 9124390 | Drift tracking feedback for communication channels | Abhijit Abhyankar, Kun-Yung Chang, Frank Lambrecht | 2015-09-01 |
| 9111608 | Strobe-offset control circuit | — | 2015-08-18 |
| 9087572 | Content addressable memory | Deepak C. Sekar, Brent Haukness, John Eric Linstadt | 2015-07-21 |