Issued Patents All Time
Showing 76–100 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9684321 | On-chip regulator with variable load compensation | Brian S. Leibowitz, Michael D. Bucher, Chaofeng Huang, Amir Amirkhany, Huy M. Nguyen +2 more | 2017-06-20 |
| 9564879 | Reference voltage generation and calibration for single-ended signaling | Barry William Daly, Kambiz Kaviani, John Eble, John Wilson | 2017-02-07 |
| 9430027 | Power-management for integrated circuits | Ian Shaeffer, Liji Gopalakrishnan | 2016-08-30 |
| 9412428 | Memory components and controllers that calibrate multiphase synchronous timing references | Thomas J. Giovannini, Scott C. Best, Ian Shaeffer | 2016-08-09 |
| 9378786 | Memory controller with phase adjusted clock for performing memory operations | Ian Shaeffer | 2016-06-28 |
| 9373384 | Integrated circuit device having programmable input capacitance | Ravindranath Kollipara, Ian Shaeffer | 2016-06-21 |
| 9304568 | Changing settings for a transient period associated with a deterministic event | Yu Chang, Kyung Suk Oh | 2016-04-05 |
| 9294317 | Equalizer-compensated AC-coupled termination | John Wilson, Wayne D. Dettloff | 2016-03-22 |
| 9166650 | Capacitive-coupled crosstalk cancellation | John Wilson | 2015-10-20 |
| 9166838 | Reference voltage generation and calibration for single-ended signaling | Barry William Daly, Kambiz Kaviani, John Eble, John Wilson | 2015-10-20 |
| 9148187 | Methods and systems for self-referencing single-ended signals | Michael D. Bucher | 2015-09-29 |
| 9098281 | Power-management for integrated circuits | Ian Shaeffer, Liji Gopalakrishnan | 2015-08-04 |
| 9046909 | On-chip regulator with variable load compensation | Brian S. Leibowitz, Michael D. Bucher, Chaofeng Huang, Amir Amirkhany, Huy M. Nguyen +2 more | 2015-06-02 |
| 8867595 | Reference voltage generation and calibration for single-ended signaling | Barry William Daly, Kambiz Kaviani, John Eble, John Wilson | 2014-10-21 |
| 8836394 | Method and apparatus for source-synchronous signaling | Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Eble, Barry William Daly +4 more | 2014-09-16 |
| 8743973 | Receiver resistor network for common-mode signaling | Brian S. Leibowitz, Jared L. Zerbe, Barry William Daly, Wayne D. Dettloff, John Eble +1 more | 2014-06-03 |
| 8618869 | Fast power-on bias circuit | Wayne D. Dettloff, John Wilson, Brian S. Leibowitz, Jared L. Zerbe, Pravin Kumar Venkatesan | 2013-12-31 |
| 8617989 | Liner property improvement | Kedar Sapre, Manuel A. Hernandez | 2013-12-31 |
| 8588280 | Asymmetric communication on shared links | Kyung Suk Oh, John Wilson, Frederick A. Ware, WooPoung KIM, Jade M. Kizer +2 more | 2013-11-19 |
| 8581920 | Utilizing masked data bits during accesses to a memory | Frederick A. Ware, John Wilson, Jade M. Kizer | 2013-11-12 |
| 8498344 | Frequency responsive bus coding | John Wilson, Aliazam Abbasfar, John Eble, Jade M. Kizer, Carl W. Werner +1 more | 2013-07-30 |
| 8462891 | Error detection and offset cancellation during multi-wire communication | Jade M. Kizer, John Wilson, Frederick A. Ware, Jared L. Zerbe | 2013-06-11 |
| 8404583 | Conformality of oxide layers along sidewalls of deep vias | Zhong Qiang Hua, Manuel A. Hernandez, Kedar Sapre | 2013-03-26 |
| 8198930 | Reducing power-supply-induced jitter in a clock-distribution circuit | Jared L. Zerbe, Brian S. Leibowitz, John Wilson, Anshuman Bhuyan, Marko Aleksic | 2012-06-12 |
| 8068357 | Memory controller with multi-modal reference pad | Frederick A. Ware, John Wilson, John Eble, Jade M. Kizer, John W. Poulton +1 more | 2011-11-29 |