Issued Patents All Time
Showing 76–100 of 257 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9973177 | Clock generator with injection-locking oscillators | Yue Lu | 2018-05-15 |
| 9923711 | Low power edge and data sampling | — | 2018-03-20 |
| 9917708 | Partial response receiver | Vladimir Stojanovic, Andrew Ho, Anthony Bessios, Bruno W. Garlepp, Grace Tsang +2 more | 2018-03-13 |
| 9912469 | Phase control block for managing multiple clock domains in systems with frequency offsets | Hae-Chang Lee, Carl W. Werner | 2018-03-06 |
| 9900189 | Methods and circuits for asymmetric distribution of channel equalization between devices | Fariborz Assaderaghi, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin | 2018-02-20 |
| 9893720 | Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid | Brian Hing-Kit Tsang | 2018-02-13 |
| 9852105 | Flash controller to provide a value that represents a parameter to a flash memory | Mark A. Horowitz, Craig E. Hampel, Alfredo Moncayo, Kevin S. Donnelly | 2017-12-26 |
| 9843315 | Data transmission using delayed timing signals | Frederick A. Ware, Ely Tsern, Brian S. Leibowitz | 2017-12-12 |
| 9843309 | Receiver with time-varying threshold voltage | Brian S. Leibowitz, Qi Lin | 2017-12-12 |
| 9806916 | Selectable-tap equalizer | Vladimir Stojanovic, Fred F. Chen | 2017-10-31 |
| 9785589 | Memory controller that calibrates a transmit timing offset | Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu +5 more | 2017-10-10 |
| 9748960 | Method and apparatus for source-synchronous signaling | Brian S. Leibowitz, Hsuan-Jung Su, John Eble, Barry William Daly, Lei Luo +4 more | 2017-08-29 |
| 9742602 | High-speed signaling systems with adaptable pre-emphasis and equalization | Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly +1 more | 2017-08-22 |
| 9735791 | Jitter-based clock selection | Brian S. Leibowitz, Masum Hossain | 2017-08-15 |
| 9735792 | Integrated circuit comprising circuitry to determine settings for an injection-locked oscillator | Masum Hossain | 2017-08-15 |
| 9660840 | Selectable-tap equalizer | Vladimir Stojanovic, Fred F. Chen | 2017-05-23 |
| 9595526 | Multi-die fine grain integrated voltage regulation | Emerson S. Fang, Jun Zhai, Shawn Searles | 2017-03-14 |
| 9568980 | Using dynamic bursts to support frequency-agile memory interfaces | Brian Hing-Kit Tsang, Barry William Daly | 2017-02-14 |
| 9565036 | Techniques for adjusting clock signals to compensate for noise | Pradeep Batra, Brian S. Leibowitz | 2017-02-07 |
| 9564911 | Integrated circuit having a multiplying injection-locked oscillator | Barry William Daly, Dustin T. Dunwell, Anthony C. Carusone, John Eble | 2017-02-07 |
| 9563228 | Clock generation for timing communications with ranks of memory devices | Ian Shaeffer, John Eble | 2017-02-07 |
| 9553745 | High-speed signaling systems with adaptable pre-emphasis and equalization | Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly +1 more | 2017-01-24 |
| 9544169 | Multiphase receiver with equalization circuitry | Bruno W. Garlepp, Pak Shing Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos +2 more | 2017-01-10 |
| 9536589 | Low-power source-synchronous signaling | Frederick A. Ware | 2017-01-03 |
| 9531391 | Frequency-agile clock multiplier | Yue Lu | 2016-12-27 |