Issued Patents All Time
Showing 51–75 of 257 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10491200 | Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid | Brian Hing-Kit Tsang | 2019-11-26 |
| 10454667 | Phase control block for managing multiple clock domains in systems with frequency offsets | Hae-Chang Lee, Carl W. Werner | 2019-10-22 |
| 10418089 | Low-power source-synchronous signaling | Frederick A. Ware | 2019-09-17 |
| 10411012 | Multi-die fine grain integrated voltage regulation | Emerson S. Fang, Jun Zhai, Shawn Searles | 2019-09-10 |
| 10404236 | Receiver with time-varying threshold voltage | Brian S. Leibowitz, Qi Lin | 2019-09-03 |
| 10404262 | Integrated circuit having a multiplying injection-locked oscillator | Barry William Daly, Dustin T. Dunwell, Anthony C. Carusone, John Eble | 2019-09-03 |
| 10401900 | Using a stuttered clock signal to reduce self-induced voltage noise | Brian S. Leibowitz | 2019-09-03 |
| 10382023 | Frequency-agile clock generator | Yue Lu | 2019-08-13 |
| 10366045 | Flash controller to provide a value that represents a parameter to a flash memory | Mark A. Horowitz, Craig E. Hampel, Alfredo Moncayo, Kevin S. Donnelly | 2019-07-30 |
| 10355888 | Selectabe-tap equalizer | Vladimir Stojanovic, Fred F. Chen | 2019-07-16 |
| 10310999 | Flash memory controller with calibrated data communication | Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu +5 more | 2019-06-04 |
| 10250240 | Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid | Brian Hing-Kit Tsang | 2019-04-02 |
| 10230379 | Downshift techniques for oscillator with feedback loop | Brian S. Leibowitz, Sanjay Pant | 2019-03-12 |
| 10225111 | Partial response receiver | Vladimir Stojanovic, Andrew Ho, Anthony Bessios, Bruno W. Garlepp, Grace Tsang +2 more | 2019-03-05 |
| 10211841 | Method and apparatus for source-synchronous signaling | Brian S. Leibowitz, Hsuan-Jung Su, John Eble, Barry William Daly, Lei Luo +4 more | 2019-02-19 |
| 10205614 | High-speed signaling systems with adaptable pre-emphasis and equalization | Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly +2 more | 2019-02-12 |
| 10205458 | Run-time output clock determination | Brian S. Leibowitz, Masum Hossain | 2019-02-12 |
| 10162772 | Clock generation for timing communications with ranks of memory devices | Ian Shaeffer, John Eble | 2018-12-25 |
| 10135427 | Receiver with time-varying threshold voltage | Brian S. Leibowitz, Qi Lin | 2018-11-20 |
| 10135647 | Methods and circuits for asymmetric distribution of channel equalization between devices | Fariborz Assaderaghi, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin | 2018-11-20 |
| 10108246 | Using dynamic bursts to support frequency-agile memory interfaces | Brian Hing-Kit Tsang, Barry William Daly | 2018-10-23 |
| 10103907 | Selectable-tap equalizer | Vladimir Stojanovic, Fred F. Chen | 2018-10-16 |
| 10056384 | Multi-die fine grain integrated voltage regulation | Emerson S. Fang, Jun Zhai, Shawn Searles | 2018-08-21 |
| 10003484 | High-speed signaling systems with adaptable pre-emphasis and equalization | Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly +1 more | 2018-06-19 |
| 9998305 | Multi-PAM output driver with distortion compensation | Bruno W. Garlepp, Pak Shing Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos +2 more | 2018-06-12 |