Issued Patents All Time
Showing 126–150 of 257 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9136826 | Integrated circuit comprising frequency change detection circuitry | Kambiz Kaviani, Kashinath Prabhu, Brian Hing-Kit Tsang | 2015-09-15 |
| 9135967 | Chip having register to store value that represents adjustment to output drive strength | Mark A. Horowitz, Craig E. Hampel, Alfredo Moncayo, Kevin S. Donnelly | 2015-09-15 |
| 9137063 | High-speed signaling systems with adaptable pre-emphasis and equalization | Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly +1 more | 2015-09-15 |
| 9135186 | Chip having port to receive value that represents adjustment to output driver parameter | Mark A. Horowitz, Craig E. Hampel, Alfredo Moncayo, Kevin S. Donnelly | 2015-09-15 |
| 9110828 | Chip having register to store value that represents adjustment to reference voltage | Mark A. Horowitz, Craig E. Hampel, Alfredo Moncayo, Kevin S. Donnelly | 2015-08-18 |
| 9110596 | Fast-wake memory | Frederick A. Ware, Brian S. Leibowitz | 2015-08-18 |
| 9106397 | Selectable-tap equalizer | Vladimir Stojanovic, Fred F. Chen | 2015-08-11 |
| 9106399 | Phase control block for managing multiple clock domains in systems with frequency offsets | Hae-Chang Lee, Carl W. Werner | 2015-08-11 |
| 9094238 | High-speed signaling systems with adaptable pre-emphasis and equalization | Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly +1 more | 2015-07-28 |
| 9077575 | Methods and circuits for asymmetric distribution of channel equalization between devices | Fariborz Assaderaghi, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin | 2015-07-07 |
| 9065628 | Frequency-agile clock multiplier | Yue Lu | 2015-06-23 |
| 9036764 | Clock recovery circuit | Masum Hossain, Myeong Jae PARK | 2015-05-19 |
| 9025678 | Partial response receiver | Vladimir Stojanovic, Mark A. Horowitz, Anthony Bessios, Andrew Ho, Jason C. Wei +2 more | 2015-05-05 |
| 8989249 | High-speed signaling systems with adaptable pre-emphasis and equalization | Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly +1 more | 2015-03-24 |
| 8948212 | Memory controller with circuitry to set memory device-specific reference voltages | Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu +5 more | 2015-02-03 |
| 8941420 | Low-latency, frequency-agile clock multiplier | Brian S. Leibowitz, Masum Hossain | 2015-01-27 |
| 8930740 | Regulation of memory IO timing using programmatic control over memory device IO timing | Scott C. Best, Brian LEIBOWITZ | 2015-01-06 |
| 8896355 | Clock multiplier with dynamically tuned lock range | Yue Lu | 2014-11-25 |
| 8890580 | Methods and circuits for reducing clock jitter | Teva J. Stone, Jihong Ren | 2014-11-18 |
| 8861667 | Clock data recovery circuit with equalizer clock calibration | Vladimir Stojanovic, Fred F. Chen | 2014-10-14 |
| 8836394 | Method and apparatus for source-synchronous signaling | Brian S. Leibowitz, Hsuan-Jung Su, John Eble, Barry William Daly, Lei Luo +4 more | 2014-09-16 |
| 8824222 | Fast-wake memory | Frederick A. Ware, Brian S. Leibowitz | 2014-09-02 |
| 8817849 | Methods and systems for transmitting data by modulating transmitter filter coefficients | Jaeha Kim, Haechang Lee, Jung-Hoon Chun | 2014-08-26 |
| 8812919 | Method and apparatus for evaluating and optimizing a signaling system | Pak Shing Chau, William Stonecypher | 2014-08-19 |
| 8812918 | Method and apparatus for evaluating and optimizing a signaling system | Pak Shing Chau, William Stonecypher | 2014-08-19 |