Issued Patents All Time
Showing 326–350 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10455698 | Load reduced memory module | Suresh Rajan | 2019-10-22 |
| 10452478 | Memory component with error-detect-correct code interface | Brent Haukness, Lawrence Lai | 2019-10-22 |
| 10453517 | High capacity memory system using controller component | Suresh Rajan, Scott C. Best | 2019-10-22 |
| 10447465 | Signaling system with adaptive timing calibration | Bret G. Stott, Craig E. Hampel | 2019-10-15 |
| 10447270 | Low power logic circuitry | John Eric Linstadt | 2019-10-15 |
| 10418089 | Low-power source-synchronous signaling | Jared L. Zerbe | 2019-09-17 |
| 10409742 | Interface for memory readout from a memory component in the event of fault | Kenneth L. Wright | 2019-09-10 |
| 10402352 | Semiconductor memory systems with on-die data buffering | Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil | 2019-09-03 |
| 10402110 | Adjustable access energy and access latency memory system and devices | John Eric Linstadt | 2019-09-03 |
| 10388337 | Memory with deferred fractional row activation | James E. Harris, Thomas Vogelsang, Ian Shaeffer | 2019-08-20 |
| 10388355 | Dual-domain memory | John Eric Linstadt | 2019-08-20 |
| 10388375 | Fast read speed memory device | Deepak C. Sekar, Gary B. Bronner | 2019-08-20 |
| 10378967 | Dual temperature band integrated circuit device | Thomas Vogelsang | 2019-08-13 |
| 10360972 | Memories and memory components with interconnected and redundant data interfaces | Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Scott C. Best, Kenneth L. Wright | 2019-07-23 |
| 10345836 | Bidirectional signaling with asymmetric termination | John Eric Linstadt | 2019-07-09 |
| 10339999 | Variable width memory module supporting enhanced error detection and correction | John Eric Linstadt, Kenneth L. Wright | 2019-07-02 |
| 10339990 | Strobe acquisition and tracking | Bret G. Stott, Ian Shaeffer, Yuanlong Wang | 2019-07-02 |
| 10331379 | Memory controller for micro-threaded memory operations | Craig E. Hampel, Wayne S. Richardson, Chad A. Bellows, Lawrence Lai | 2019-06-25 |
| 10331193 | Signaling interface with phase and framing calibration | Robert E. Palmer, John W. Poulton, Andrew M. Fuller | 2019-06-25 |
| 10325645 | Memory controller with clock-to-strobe skew compensation | — | 2019-06-18 |
| 10320496 | Periodic calibration for communication channels by drift tracking | Craig E. Hampel, Richard E. Perego | 2019-06-11 |
| 10305674 | Communication channel calibration for drift conditions | Richard E. Perego, Craig E. Hampel | 2019-05-28 |
| 10268619 | Cross-threaded memory system | Kishore Ven Kasamsetty | 2019-04-23 |
| 10268607 | Memory module threading with staggered data transfers | Hongzhong Zheng | 2019-04-23 |
| 10262750 | Testing through-silicon-vias | Thomas Vogelsang, William N. Ng | 2019-04-16 |