Issued Patents All Time
Showing 126–150 of 151 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6689702 | High dielectric constant metal oxide gate dielectrics | Gang Bai, David B. Fraser, Brian S. Doyle, Chunlin Liang | 2004-02-10 |
| 6650204 | Resonator frequency correction by modifying support structures | Qing Ma, Valluri Rao | 2003-11-18 |
| 6630871 | Center-mass-reduced microbridge structures for ultra-high frequency MEM resonator | Qing Ma | 2003-10-07 |
| 6621137 | MEMS device integrated chip package, and method of making same | Qing Ma, Valluri Rao | 2003-09-16 |
| 6600389 | Tapered structures for generating a set of resonators with systematic resonant frequencies | Qing Ma | 2003-07-29 |
| 6596609 | Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer | Brian S. Doyle | 2003-07-22 |
| 6593672 | MEMS-switched stepped variable capacitor and method of making same | Qing Ma, Valluri Rao | 2003-07-15 |
| 6573822 | Tunable inductor using microelectromechanical switches | Qing Ma, Valluri Rao | 2003-06-03 |
| 6570468 | Resonator frequency correction by modifying support structures | Qing Ma, Valluri Rao | 2003-05-27 |
| 6570220 | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition | Brian S. Doyle | 2003-05-27 |
| 6528856 | High dielectric constant metal oxide gate dielectrics | Gang Bai, David B. Fraser, Brian S. Doyle, Chunlin Liang | 2003-03-04 |
| 6479921 | Micro-electromechanical structure resonator, method of making, and method of using | Qing Ma | 2002-11-12 |
| 6445106 | Micro-electromechanical structure resonator, method of making, and method of using | Qing Ma | 2002-09-03 |
| 6355534 | Variable tunable range MEMS capacitor | Qing Ma | 2002-03-12 |
| 6300221 | Method of fabricating nanoscale structures | Brian Roberds, Brian S. Doyle | 2001-10-09 |
| 6277765 | Low-K Dielectric layer and method of making same | Brian S. Doyle, Chien Chiang, Mark Thiec-Hien Tran | 2001-08-21 |
| 6197676 | Method of forming metal lines | Brian S. Doyle | 2001-03-06 |
| 6187694 | Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer | Brian S. Doyle | 2001-02-13 |
| 6162696 | Method of fabricating a feature in an integrated circuit using a two mask process with a single edge definition layer | Brian S. Doyle | 2000-12-19 |
| 6121093 | Method of making asymmetrical transistor structures | Brian S. Doyle | 2000-09-19 |
| 6063688 | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition | Brian S. Doyle | 2000-05-16 |
| 6022815 | Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique | Brian S. Doyle, Chunlin Liang, Qi-De Qian | 2000-02-08 |
| 5918132 | Method for narrow space formation and self-aligned channel implant | Qi-De Qian | 1999-06-29 |
| 5891805 | Method of forming contacts | Brian S. Doyle | 1999-04-06 |
| 5536684 | Process for formation of epitaxial cobalt silicide and shallow junction of silicon | M. Lawrence A. Dass, David B. Fraser | 1996-07-16 |