Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof

Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof

US Patent 10256248 · Granted Apr 9, 2019

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Keyboard folio2025
Three-dimensional memory device including laterally separated source lines and m2025
Bonded assembly containing conductive via structures extending through word line2025
Field effect transistors with reduced gate fringe area and method of making the 2025
Non-volatile memory with inter-die connection2025
Three-dimensional memory device containing memory opening monitoring area and me2025
X-direction divided sub-block mode in NAND2025
Stacked column floorplan for NAND2025
Channel pre-charge process in a memory device2025
Three-dimensional memory device with high contact via density and methods of for2025
Three-dimensional memory device with high contact via density and methods of for2025
Three-dimensional nor array and method of making the same2025