Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8078942 | Register error correction of speculative data in an out-of-order processor | Christopher H. Olson | 2011-12-13 |
| 7937556 | Minimizing TLB comparison size | Manish K. Shah, Gregory F. Grohoski | 2011-05-03 |
| 7861063 | Delay slot handling in a processor | Robert T. Golla, Jama I. Barreh | 2010-12-28 |
| 7779238 | Method and apparatus for precisely identifying effective addresses associated with hardware events | Nicolai Kosche, Gregory F. Grohoski | 2010-08-17 |
| 7702887 | Performance instrumentation in a fine grain multithreaded multicore processor | Gregory F. Grohoski, Yue Chang | 2010-04-20 |
| 7676655 | Single bit control of threads in a multithreaded multicore processor | — | 2010-03-09 |
| 7543132 | Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes | Greg F. Grohoski, Ashley Saulsbury, Manish K. Shah, Rabin Sugumar, Mark Debbage +1 more | 2009-06-02 |
| 7454666 | Real-time address trace generation | Joseph T. Rahmeh, Gregory F. Grohoski | 2008-11-18 |
| 7454590 | Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores | Manish K. Shah, Gregory F. Grohoski | 2008-11-18 |
| 7430643 | Multiple contexts for efficient use of translation lookaside buffer | William J. Kucharski, Roman Zajcew, Ashley Saulsbury, Quinn A. Jacobson | 2008-09-30 |
| 7426630 | Arbitration of window swap operations | Jike Chong, Robert T. Golla | 2008-09-16 |
| 7392399 | Methods and systems for efficiently integrating a cryptographic co-processor | Gregory F. Grohoski, Michael Wong, Leslie D. Kohn | 2008-06-24 |
| 7383415 | Hardware demapping of TLBs shared by multiple threads | Manish K. Shah, Gregory F. Grohoski | 2008-06-03 |
| 7373489 | Apparatus and method for floating-point exception prediction and recovery | Jeffrey S. Brooks, Rabin Sugumar | 2008-05-13 |
| 7370243 | Precise error handling in a fine grain multithreaded multicore processor | Gregory F. Grohoski, Ricky C. Hetherington, Robert M. Maier | 2008-05-06 |
| 7366829 | TLB tag parity checking without CAM read | Mark Luttrell | 2008-04-29 |
| 7350053 | Software accessible fast VA to PA translation | Rabin Sugumar, Robert T. Golla | 2008-03-25 |
| 7343474 | Minimal address state in a fine grain multithreaded processor | Robert T. Golla, Jama I. Barreh | 2008-03-11 |
| 7274706 | Methods and systems for processing network data | Tung Nguyen, Fong Pong, Syrus Ziai, Al Chang, Greg F. Grohoski | 2007-09-25 |
| 7178005 | Efficient implementation of timers in a multithreaded processor | Ashley Saulsbury, John G. Johnson | 2007-02-13 |
| 6976205 | Method and apparatus for calculating TCP and UDP checksums while preserving CPU resources | Syrus Ziai, Craig Robson, Ryan Patrick Donohue, Fong Pong | 2005-12-13 |
| 6857083 | Method and system for triggering a debugging unit | Michael Stephen Floyd, Larry Scott Leitner | 2005-02-15 |
| 6785847 | Soft error detection in high speed microprocessors | Peter Juergen Klim | 2004-08-31 |
| 6701484 | Register file with delayed parity check | Peter Juergen Klim | 2004-03-02 |
| 6658534 | Mechanism to reduce instruction cache miss penalties and methods therefor | Steven Wayne White, Hung Q. Le, Kurt A. Feiste | 2003-12-02 |