Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12292834 | Cache prefetching | Vladimir Vasekin, Vincent Rezard, Cedric Denis Robert Airaud | 2025-05-06 |
| 12277028 | Error correction code | Siddharth Gupta | 2025-04-15 |
| 12009041 | Apparatus and method for detecting errors in a memory device | Siddharth Gupta, Cyrille Dray, Luc Palau, Sachin Gulyani | 2024-06-11 |
| 11579889 | Programmable instruction buffering for accumulating a burst of instructions | Jatin Bhartia, Kauser Yakub Johar | 2023-02-14 |
| 11579879 | Processing pipeline with first and second processing modes having different performance or energy consumption characteristics | Max John Batley, Simon John Craske, Ian Michael Caulfield, Peter Richard Greenhalgh, Allan John Skillman | 2023-02-14 |
| 11275607 | Improving the responsiveness of an apparatus to certain interrupts | Peter Richard Greenhalgh | 2022-03-15 |
| 11194577 | Instruction issue according to in-order or out-of-order execution modes | Simon John Craske, Vladimir Vasekin | 2021-12-07 |
| 11074080 | Apparatus and branch prediction circuitry having first and second branch prediction schemes, and method | Peter Richard Greenhalgh, Simon John Craske, Ian Michael Caulfield, Max John Batley, Allan John Skillman | 2021-07-27 |
| 11055440 | Handling access attributes for data accesses | Simon John Craske | 2021-07-06 |
| 10997076 | Asymmetric coherency protocol for first and second processing circuitry having different levels of fault protection or fault detection | Simon John Craske | 2021-05-04 |
| 10963250 | Selectively suppressing time intensive instructions based on a control value | Simon John Craske | 2021-03-30 |
| 10866810 | Programmable instruction buffering of a burst of instructions including a pending data write to a given memory address and a subsequent data read of said given memory address | Jatin Bhartia, Kauser Yakub Johar | 2020-12-15 |
| 10817369 | Apparatus and method for increasing resilience to faults | Reiley Jeyapaul, Balaji Venu, Xabier Iturbe, Emre Ozer | 2020-10-27 |
| 10705587 | Mode switching in dependence upon a number of active threads | Peter Richard Greenhalgh, Simon John Craske, Ian Michael Caulfield, Max John Batley, Allan John Skillman | 2020-07-07 |
| 10620953 | Instruction prefetch halting upon predecoding predetermined instruction types | Kauser Yakub Johar | 2020-04-14 |
| 10402203 | Determining a predicted behaviour for processing of instructions | Max John Batley, Simon John Craske, Ian Michael Caulfield, Peter Richard Greenhalgh, Allan John Skillman | 2019-09-03 |
| 10354092 | Handling access attributes for data accesses | Simon John Craske | 2019-07-16 |
| 10303566 | Apparatus and method for checking output data during redundant execution of instructions | Emre Ozer, Balaji Venu, Xabier Iturbe | 2019-05-28 |
| 10296349 | Allocating a register to an instruction using register index information | Vladimir Vasekin, Chiloda Ashan Senerath Pathirane, Andrew James Antony Lees | 2019-05-21 |
| 10289332 | Apparatus and method for increasing resilience to faults | Xabier Iturbe, Emre Ozer, Balaji Venu | 2019-05-14 |
| 9977679 | Apparatus and method for suspending execution of a thread in response to a hint instruction | Ian Michael Caulfield, Robert Gwilym Dimond | 2018-05-22 |
| 9952871 | Controlling execution of instructions for a processing pipeline having first out-of order execution circuitry and second execution circuitry | Ian Michael Caulfield, Peter Richard Greenhalgh, Simon John Craske, Max John Batley, Allan John Skillman | 2018-04-24 |
| 9940137 | Processor exception handling using a branch target cache | Matthew Lee Winrow | 2018-04-10 |
| 9886276 | System register access | Loïc Pierron | 2018-02-06 |
| 9836403 | Dynamic cache allocation policy adaptation in a data processing apparatus | Kauser Yakub Johar, Zemian Hughes | 2017-12-05 |