Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12292834 | Cache prefetching | Vincent Rezard, Antony John Penton, Cedric Denis Robert Airaud | 2025-05-06 |
| 11947460 | Treating multiple cache lines as a merged cache line to store multiple blocks of data | David Michael Bull, Vincent Rezard, Anton Antonov | 2024-04-02 |
| 11429393 | Apparatus and method for supporting out-of-order program execution of instructions | Ian Michael Caulfield, Chiloda Ashan Senerath Pathirane | 2022-08-30 |
| 11416252 | Program instruction fusion | Chiloda Ashan Senerath Pathirane, Jungsoo KIM, Alexei Fedorov | 2022-08-16 |
| 11409532 | Selecting instructions for a value predictor | David Michael Bull, Sanghyun Park, Alexei Fedorov | 2022-08-09 |
| 11403105 | Detecting misprediction when an additional branch direction prediction determined using value prediction is considered more accurate than an initial branch direction prediction | David Michael Bull, Frederic Claude Marie Piry, Alexei Fedorov | 2022-08-02 |
| 11366668 | Method and apparatus for comparing predicated load value with masked load value | David Michael Bull, Sanghyun Park, Alexei Fedorov | 2022-06-21 |
| 11194577 | Instruction issue according to in-order or out-of-order execution modes | Antony John Penton, Simon John Craske | 2021-12-07 |
| 10719329 | Apparatus and method for using predicted result values | David Michael Bull, Chiloda Ashan Senerath Pathirane, Alexei Fedorov | 2020-07-21 |
| 10620962 | Appratus and method for using predicted result values | David Michael Bull, Alexei Fedorov | 2020-04-14 |
| 10296349 | Allocating a register to an instruction using register index information | Antony John Penton, Chiloda Ashan Senerath Pathirane, Andrew James Antony Lees | 2019-05-21 |
| 9645824 | Branch target address cache using hashed fetch addresses | Allan John Skillman, Chiloda Ashan Senerath Pathirane, Jean-Baptiste Brelot | 2017-05-09 |
| 8954715 | Thread selection for multithreaded processing | Andrew Christopher Rose, Allan John Skillman, Antony John Penton | 2015-02-10 |
| 8010774 | Breakpointing on register access events or I/O port access events | Andrei Kapustin, Yuri Ledvik | 2011-08-30 |
| 7900019 | Data access target predictions in a data processing system | Andrew Christopher Rose, David Hart, Javed Osmany | 2011-03-01 |
| 7877587 | Branch prediction within a multithreaded processor | Stuart David Biles, Yuri Levdik, Andrei Kapustin | 2011-01-25 |
| 7802080 | Null exception handling | David John Butcher, Stephen John Hill, Hedley James Francis, Andrew Christopher Rose | 2010-09-21 |
| 7707390 | Instruction issue control within a multi-threaded in-order superscalar processor | Emre Ozer, Stuart David Biles | 2010-04-27 |
| 7533241 | Variable size cache memory support within an integrated circuit | Florent Begon, Andrew Christophe Rose, Nicolas Chaussade | 2009-05-12 |
| 7529889 | Data processing apparatus and method for performing a cache lookup in an energy efficient manner | Stuart David Biles | 2009-05-05 |
| 7489752 | Synchronisation of signals between asynchronous logic | Antony John Penton, Andrew Christopher Rose, Paul Stanley Hughes, Christopher Wrigley | 2009-02-10 |
| 7447871 | Data access program instruction encoding | David James Seal | 2008-11-04 |
| 7447883 | Allocation of branch target cache resources in dependence upon program instructions within an instruction queue | Stuart David Biles, Andrew Christopher Rose, Wilco Dijkstra | 2008-11-04 |
| 7386709 | Controlling execution of a block of program instructions within a computer processing system | — | 2008-06-10 |
| 7360061 | Program instruction decompression and compression techniques | Andrew Christopher Rose | 2008-04-15 |