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Processing pipeline with first and second processing modes having different performance or energy consumption characteristics |
Max John Batley, Simon John Craske, Ian Michael Caulfield, Peter Richard Greenhalgh, Antony John Penton |
2023-02-14 |
| 11226828 |
Wakeup interrupt controller |
Peter Vrabel |
2022-01-18 |
| 11074080 |
Apparatus and branch prediction circuitry having first and second branch prediction schemes, and method |
Peter Richard Greenhalgh, Simon John Craske, Ian Michael Caulfield, Max John Batley, Antony John Penton |
2021-07-27 |
| 10705587 |
Mode switching in dependence upon a number of active threads |
Peter Richard Greenhalgh, Simon John Craske, Ian Michael Caulfield, Max John Batley, Antony John Penton |
2020-07-07 |
| 10402203 |
Determining a predicted behaviour for processing of instructions |
Max John Batley, Simon John Craske, Ian Michael Caulfield, Peter Richard Greenhalgh, Antony John Penton |
2019-09-03 |
| 9952871 |
Controlling execution of instructions for a processing pipeline having first out-of order execution circuitry and second execution circuitry |
Ian Michael Caulfield, Peter Richard Greenhalgh, Simon John Craske, Max John Batley, Antony John Penton |
2018-04-24 |
| 9710359 |
Executing debug program instructions on a target apparatus processing pipeline |
Chiloda Ashan Senerath Pathirane |
2017-07-18 |
| 9665494 |
Parallel lookup in first and second value stores |
Chiloda Ashan Senerath Pathirane |
2017-05-30 |
| 9658919 |
Malfunction escalation |
Chiloda Ashan Senerath Pathirane |
2017-05-23 |
| 9645824 |
Branch target address cache using hashed fetch addresses |
Vladimir Vasekin, Chiloda Ashan Senerath Pathirane, Jean-Baptiste Brelot |
2017-05-09 |
| 8954715 |
Thread selection for multithreaded processing |
Vladimir Vasekin, Andrew Christopher Rose, Antony John Penton |
2015-02-10 |
| 7925867 |
Pre-decode checking for pre-decoded instructions that cross cache line boundaries |
Peter Richard Greenhalgh, Max Zardini, Daniel Paul Schostak |
2011-04-12 |