Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8977820 | Handling of hard errors in a cache of a data processing apparatus | Alex James Waugh, Andrew Christopher Rose, Paul Stanley Hughes | 2015-03-10 |
| 8954715 | Thread selection for multithreaded processing | Vladimir Vasekin, Andrew Christopher Rose, Allan John Skillman | 2015-02-10 |
| 8756377 | Area and power efficient data coherency maintenance | Simon John Craske, Loïc Pierron, Andrew Christopher Rose | 2014-06-17 |
| 8661232 | Register state saving and restoring | Simon Axford | 2014-02-25 |
| 8621336 | Error correction in a set associative storage device | Simon John Craske, Andrew Christopher Rose, Paul Stanley Hughes, Richard York, Simon Andrew Ford +2 more | 2013-12-31 |
| 8499017 | Apparatus and method for performing fused multiply add floating point operation | Simon John Craske, Ian Michael Caulfield | 2013-07-30 |
| 8484508 | Data processing apparatus and method for providing fault tolerance when executing a sequence of data processing operations | Simon Andrew Ford, Andrew Christopher Rose | 2013-07-09 |
| 8374098 | Check data encoding using parallel lane encoders | Martinus Cornelis Wezelenburg, Ken Wong | 2013-02-12 |
| 8356119 | Performance by reducing transaction request ordering requirements | Mittu Xavier Kocherry, Simon John Craske | 2013-01-15 |
| 8190973 | Apparatus and method for error correction of data values in a storage device | Andrew Christopher Rose, Paul Stanley Hughes | 2012-05-29 |
| 8108730 | Debugging a multiprocessor system that switches between a locked mode and a split mode | Chiloda Ashan Senerath Pathirane | 2012-01-31 |
| 8051323 | Auxiliary circuit structure in a split-lock dual processor system | Chiloda Ashan Senerath Pathirane | 2011-11-01 |
| 7489752 | Synchronisation of signals between asynchronous logic | Vladimir Vasekin, Andrew Christopher Rose, Paul Stanley Hughes, Christopher Wrigley | 2009-02-10 |
| 7085874 | Synchronous/asynchronous bridge circuit for improved transfer of data between two circuits | Richard Roy Grisenthwaite | 2006-08-01 |