Issued Patents All Time
Showing 76–100 of 116 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5848012 | Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system | Takahiro Tsuruda | 1998-12-08 |
| 5844295 | Semiconductor device having a fuse and an improved moisture resistance | Kazutami Arimoto | 1998-12-01 |
| 5838627 | Arrangement of power supply and data input/output pads in semiconductor memory device | Shigeki Tomishima, Mikio Asakura, Kazutami Arimoto | 1998-11-17 |
| 5831924 | Synchronous semiconductor memory device having a plurality of banks distributed in a plurality of memory arrays | Yasuhiko Nitta | 1998-11-03 |
| 5831921 | Semiconductor memory device having signal generating circuitry for sequentially refreshing memory cells in each memory cell block in a self-refresh mode | — | 1998-11-03 |
| 5825705 | Semiconductor memory device having self-refreshing function | Kazutami Arimoto | 1998-10-20 |
| 5815428 | Semiconductor memory device having hierarchical bit line structure | Takahiro Tsuruda | 1998-09-29 |
| 5812490 | Synchronous dynamic semiconductor memory device capable of restricting delay of data output timing | — | 1998-09-22 |
| 5757175 | Constant current generating circuit | Fukashi Morishita, Tsukasa Ooishi, Kyoji Yamasaki | 1998-05-26 |
| 5726946 | Semiconductor integrated circuit device having hierarchical power source arrangement | Tadato Yamagata, Kazutami Arimoto | 1998-03-10 |
| 5703522 | Switched substrate bias for MOS-DRAM circuits | Kazutami Arimoto | 1997-12-30 |
| 5696727 | Semiconductor memory device provided with sense amplifier capable of high speed operation with low power consumption | Kazutami Arimoto, Shigeki Tomishima | 1997-12-09 |
| 5694364 | Semiconductor integrated circuit device having a test mode for reliability evaluation | Fukashi Morishita, Kazutami Arimoto | 1997-12-02 |
| 5687123 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto +1 more | 1997-11-11 |
| 5682343 | Hierarchical bit line arrangement in a semiconductor memory | Shigeki Tomishima, Mikio Asakura, Kazuyasu Fujishima | 1997-10-28 |
| 5666315 | Semiconductor memory device having a redundancy function suppressible of leakage current from a defective memory cell | Kazutami Arimoto | 1997-09-09 |
| 5659517 | Semiconductor memory device with an improved hierarchical power supply line configuration | Kazutami Arimoto | 1997-08-19 |
| 5652726 | Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system | Takahiro Tsuruda | 1997-07-29 |
| 5652725 | Semiconductor memory device having a redundant row and a redundant column which can be accessed prior to substitution | Katsuhiro Suma, Yasuhiko Tsukikawa | 1997-07-29 |
| 5646900 | Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device | Kazutami Arimoto | 1997-07-08 |
| 5633831 | Semiconductor memory device having self-refreshing function | Kazutami Arimoto | 1997-05-27 |
| 5610533 | Switched substrate bias for logic circuits | Kazutami Arimoto | 1997-03-11 |
| 5604710 | Arrangement of power supply and data input/output pads in semiconductor memory device | Shigeki Tomishima, Mikio Asakura, Kazutami Arimoto | 1997-02-18 |
| 5587959 | Semiconductor memory device | — | 1996-12-24 |
| 5568440 | Semiconductor memory device having self-refreshing function | Kazutami Arimoto | 1996-10-22 |