Issued Patents All Time
Showing 101–116 of 116 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5504713 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Kazuyasu Fujishima | 1996-04-02 |
| 5408140 | Substrate potential generating circuit generating substrate potential of lower level and semiconductor device including the same | Shinji Kawai, Yoshito Nakaoka | 1995-04-18 |
| 5400290 | Semiconductor device allowing accurate characteristics test | Katsuhiro Suma, Yukinobu Adachi | 1995-03-21 |
| 5321657 | Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages | Kazutami Arimoto, Kazuyasu Fujishima, Hideto Hidaka, Tsukasa Ohishi | 1994-06-14 |
| 5315548 | Column selecting circuit in semiconductor memory device | Tsukasa Ooishi, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai +4 more | 1994-05-24 |
| 5289417 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Kazuyasu Fujishima | 1994-02-22 |
| 5267214 | Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory device and operating method therefor | Kazuyasu Fujishima, Yoshio Matsuda, Kazutami Arimoto, Tsukasa Ooishi | 1993-11-30 |
| 5249155 | Semiconductor device incorporating internal voltage down converting circuit | Kazutami Arimoto, Hideto Hidaka, Mikio Asakura, Masanori Hayashikoshi, Shinji Kawai +1 more | 1993-09-28 |
| 5185744 | Semiconductor memory device with test circuit | Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Ooishi | 1993-02-09 |
| 5184327 | Semiconductor memory device having on-chip test circuit and method for testing the same | Yoshio Matsuda, Kazutami Arimoto, Tsukasa Ooishi, Kazuyasu Fujishima | 1993-02-02 |
| 5136543 | Data descrambling in semiconductor memory device | Yoshio Matsuda, Kazuyasu Fujishima, Kazutami Arimoto, Tsukasa Oishi | 1992-08-04 |
| 5088064 | Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout | — | 1992-02-11 |
| 5088063 | Semiconductor memory device having on-chip test circuit | Yoshio Matsuda, Kazutami Arimoto, Tsukasa Ooishi, Kazuyasu Fujishima | 1992-02-11 |
| 5060230 | On chip semiconductor memory arbitrary pattern, parallel test apparatus and method | Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Ooishi | 1991-10-22 |
| 5022007 | Test signal generator for semiconductor integrated circuit memory and testing method thereof | Kazutami Arimoto, Yoshio Matsuda, Tsukasa Ooishi, Kazuyasu Fujishima | 1991-06-04 |
| 4977542 | Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout | Yoshio Matsuda, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto | 1990-12-11 |