Issued Patents All Time
Showing 51–75 of 116 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6150728 | Semiconductor memory device having a pad arrangement with reduced occupying area | Kazutami Arimoto | 2000-11-21 |
| 6134171 | Semiconductor integrated circuit device having hierarchical power source arrangement | Tadato Yamagata, Kazutami Arimoto | 2000-10-17 |
| 6097180 | Voltage supply circuit and semiconductor device including such circuit | Masanori Hayashikoshi | 2000-08-01 |
| 6075732 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Kazuyasu Fujishima | 2000-06-13 |
| 6038183 | Semiconductor memory device having burn-in mode operation stably accelerated | — | 2000-03-14 |
| 6011428 | Voltage supply circuit and semiconductor device including such circuit | Masanori Hayashikoshi | 2000-01-04 |
| 6004834 | Method of manufacturing semiconductor device having a fuse | Kazutami Arimoto | 1999-12-21 |
| 5987619 | Input signal phase compensation circuit capable of reliably obtaining external data | Takeshi Hamamoto | 1999-11-16 |
| 5982698 | Multi-bank system semiconductor memory device capable of operating at high speed | — | 1999-11-09 |
| 5982678 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Kazuyasu Fujishima | 1999-11-09 |
| 5969420 | Semiconductor device comprising a plurality of interconnection patterns | Shigehiro Kuge, Kazutami Arimoto, Kazuyasu Fujishima | 1999-10-19 |
| 5966340 | Semiconductor memory device having hierarchical word line structure | Takeshi Fujino | 1999-10-12 |
| 5959927 | Semiconductor integrated circuit device having hierarchical power source arrangement | Tadato Yamagata, Kazutami Arimoto | 1999-09-28 |
| 5949731 | Semiconductor memory device having burn-in mode operation stably accelerated | — | 1999-09-07 |
| 5943273 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto +1 more | 1999-08-24 |
| 5917765 | Semiconductor memory device capable of burn in mode operation | Fukashi Morishita | 1999-06-29 |
| 5910927 | Memory device and sense amplifier control device | Takeshi Hamamoto | 1999-06-08 |
| 5909046 | Semiconductor integrated circuit device having stable input protection circuit | Tetsushi Tanizaki, Fukashi Morishita, Kazutami Arimoto | 1999-06-01 |
| 5896328 | Semiconductor memory device allowing writing of desired data to a storage node of a defective memory cell | Tetsushi Tanizaki | 1999-04-20 |
| 5894448 | Semiconductor memory device having hierarchy control circuit architecture of master/local control circuits permitting high speed accessing | Teruhiko Amano | 1999-04-13 |
| 5894440 | Semiconductor memory device and data transferring structure and method therein | Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Ooishi | 1999-04-13 |
| RE36089 | Column selecting circuit in semiconductor memory device | Tsukasa Ooishi, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai +4 more | 1999-02-09 |
| RE36027 | Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages | Kazutami Arimoto, Kazuyasu Fujishima, Hideto Hidaka, Tsukasa Ohishi | 1999-01-05 |
| 5856951 | Semiconductor memory device with an improved hierarchical power supply line configuration | Kazutami Arimoto | 1999-01-05 |
| 5854561 | Switched substrate bias for MOS DRAM circuits | Kazutami Arimoto | 1998-12-29 |