Issued Patents All Time
Showing 76–90 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6128641 | Data processing unit with hardware assisted context switching capability | Roger D. Arnold, Bruce Holmer, Vojin G. Oklobdzija, Eric Chesters | 2000-10-03 |
| 6118368 | Electric control device | Peter Rohm, Patrick Leteinturier | 2000-09-12 |
| 6085315 | Data processing device with loop pipeline | Venkat Mattela, Eric Chesters, Muhammad Afsar | 2000-07-04 |
| 6076159 | Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline | Ole H. Moller, Gigy Baror | 2000-06-13 |
| 6041387 | Apparatus for read/write-access to registers having register file architecture in a central processing unit | Roger D. Arnold | 2000-03-21 |
| 5781746 | Microprocessor with multiple bus configurations | — | 1998-07-14 |
| 5704048 | Integrated microprocessor with internal bus and on-chip peripheral | Werner Boening | 1997-12-30 |
| 5454090 | Apparatus for furnishing instructions in a microprocessor with a multi-stage pipeline processing unit for processing instruction phase and having a memory and at least three additional memory units | Mark Poret, Karl-Heinz Mattheis, Javier V. Magana, Christoph Meinhold | 1995-09-26 |
| 5218703 | Circuit configuration and method for priority selection of interrupts for a microprocessor | Mark Poret, Karl-Heinz Mattheis | 1993-06-08 |
| 5138640 | Circuit configuration for improving the resolution of successive pulsed signals over time | Karl-Heinz Mattheis, Christoph Meinhold, Steffen Storandt | 1992-08-11 |
| 4942559 | Counter/timer circuit for a microcontroller | Mark Poret, Karl-Heinz Mattheis, Javier V. Magana, Christoph Meinhold | 1990-07-17 |
| 4926323 | Streamlined instruction processor | Gigy Baror, Brian W. Case, Philip M. Freidin, Smeeta Gupta, William M. Johnson +4 more | 1990-05-15 |
| 4777587 | System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses | Brian W. Case, Cheng-Gang Kong, Ole H. Moller | 1988-10-11 |
| 4777588 | General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance | Brian W. Case, William M. Johnson, Cheng-Gang Kong, Ole H. Moller | 1988-10-11 |
| 4734852 | Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor | William M. Johnson, Cheng-Gang Kong, Ole H. Moller | 1988-03-29 |