Issued Patents All Time
Showing 201–225 of 226 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9355730 | Mapping between program states and data patterns | Patrick R. Khayat, Mustafa N. Kaynak, Zhenlei Shen | 2016-05-31 |
| 9324370 | Identifying a defect in a data-storage medium | Shayan Srinivasa Garani | 2016-04-26 |
| 9268629 | Dual mapping between program states and data patterns | Patrick R. Khayat, Mustafa N. Kaynak | 2016-02-23 |
| 9229848 | Determining soft data for fractional digit memory cells | Patrick R. Khayat, Mustafa N. Kaynak | 2016-01-05 |
| 9190174 | Determining soft data from a hard read | Patrick R. Khayat, Mustafa N. Kaynak | 2015-11-17 |
| 9116822 | Stopping criteria for layered iterative error correction | Mustafa N. Kaynak, William H. Radke, Patrick R. Khayat | 2015-08-25 |
| 9081674 | Dual mapping between program states and data patterns | Patrick R. Khayat, Mustafa N. Kaynak | 2015-07-14 |
| 9065483 | Determining soft data using a classification code | Patrick R. Khayat, Mustafa N. Kaynak | 2015-06-23 |
| 9064575 | Determining whether a memory cell state is in a valley between adjacent data states | Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth | 2015-06-23 |
| 9021342 | Methods to improve ACS performance | Lun Bin Huang | 2015-04-28 |
| 8977808 | Mapping between program states and data patterns | Patrick R. Khayat, Mustafa N. Kaynak, Zhenlei Shen | 2015-03-10 |
| 8913336 | Constrained on-the-fly interleaver address generator circuits, systems, and methods | Shayan Srinivasa Garani, Sudha Thipparthi | 2014-12-16 |
| 8788743 | Mapping between program states and data patterns | Patrick R. Khayat, Mustafa N. Kaynak, Zhenlei Shen | 2014-07-22 |
| 8694877 | Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method | Lun Bin Huang, Alessandro Risso | 2014-04-08 |
| 8625220 | Constrained on-the-fly interleaver address generator circuits, systems, and methods | Shayan Garani Srinivasa, Sudha Thipparthi | 2014-01-07 |
| 8379339 | Closely coupled vector sequencers for a read channel pipeline | Alessandro Risso, Dillip K. Dash | 2013-02-19 |
| 8290102 | Adaptive data dependent noise prediction (ADDNP) | Mustafa N. Kaynak, Stefano Valle, Shayan Srinivasa Garani | 2012-10-16 |
| 8255768 | Interlaced iterative system design for 1K-byte block with 512-byte LDPC codewords | Xinde Hu, Shayan Srinivasa Garani, Anthony Dwayne Weathers, Richard David Barndt | 2012-08-28 |
| 8055973 | Channel constrained code aware interleaver | Shayan Srinivasa Garani, Nicholas J. Richardson, Xinde Hu | 2011-11-08 |
| 7600096 | Coprocessor extension architecture built using a novel split-instruction transaction model | Alexander Driker | 2009-10-06 |
| 7290089 | Executing cache instructions in an increased latency mode | Andrew Cofler, Lionel Chaverot | 2007-10-30 |
| 7290081 | Apparatus and method for implementing a ROM patch using a lockable cache | Alessandro Risso | 2007-10-30 |
| 7277958 | Re-assembly of streaming files from separate connections | Randall M. Chung, Maged Bishay, Michael Zelevinsky | 2007-10-02 |
| 6754807 | System and method for managing vertical dependencies in a digital signal processor | Alexander Driker | 2004-06-22 |
| 6671799 | System and method for dynamically sizing hardware loops and executing nested loops in a digital signal processor | — | 2003-12-30 |