Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12119051 | Memory array reset read operation | Jeremy Binfet, Mark A. Helm, William C. Filipiak | 2024-10-15 |
| 12111725 | Read retry scratch space | Rahul Mitchell Jairaj, Terry M. Grunzke | 2024-10-08 |
| 11710525 | Apparatus for establishing a negative body potential in a memory cell | Koji Sakui, Toru Tanzawa, Jeremy Binfet | 2023-07-25 |
| 11586498 | Read retry scratch space | Rahul Mitchell Jairaj, Terry M. Grunzke | 2023-02-21 |
| 11423976 | Memory array reset read operation | Jeremy Binfet, Mark A. Helm, William C. Filipiak | 2022-08-23 |
| 10916313 | Apparatus and methods including establishing a negative body potential in a memory cell | Koji Sakui, Toru Tanzawa, Jeremy Binfet | 2021-02-09 |
| 10685702 | Memory array reset read operation | Jeremy Binfet, Mark A. Helm, William C. Filipiak | 2020-06-16 |
| 10453538 | Apparatus and methods including establishing a negative body potential in a memory cell | Koji Sakui, Toru Tanzawa, Jeremy Binfet | 2019-10-22 |
| 10049750 | Methods including establishing a negative body potential in a memory cell | Koji Sakui, Toru Tanzawa, Jeremy Binfet | 2018-08-14 |
| 9543000 | Determining soft data for combinations of memory cells | Violante Moschiano, Tommaso Vali | 2017-01-10 |
| 9230661 | Determining soft data for combinations of memory cells | Violante Moschiano, Tommaso Vali | 2016-01-05 |
| 9007867 | Loading trim address and trim data pairs | Violante Moschiano | 2015-04-14 |
| 8737139 | Determining soft data for combinations of memory cells | Violante Moschiano, Tommaso Vali | 2014-05-27 |
| 8094508 | Memory block testing | Scott N. Gatzemeier, Joemar Sinipete, Nevil N. Gajera | 2012-01-10 |
| 7567472 | Memory block testing | Scott N. Gatzemeier, Joemar Sinipete, Nevil N. Gajera | 2009-07-28 |
| 7512507 | Die based trimming | Scott N. Gatzemeier, Joemar Sinipete, Robert J. Ringhofer, Nevil N. Gajera | 2009-03-31 |
| 6016561 | Output data compression scheme for use in testing IC memories | Fariborz F. Roohparvar, Allahyar Vahidi Mowlavi, Gregory L. Cowan | 2000-01-18 |
| 5787097 | Output data compression scheme for use in testing IC memories | Fariborz F. Roohparvar, Allahyar Vahidi Mowlavi, Gregory L. Cowan | 1998-07-28 |
| 5414376 | Programmable logic device macrocell having exclusive lines for feedback and external input, and a node which is selectively shared for registered output and external input | — | 1995-05-09 |
| 5384500 | Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes | Paul S. Zagar | 1995-01-24 |
| 5331227 | Programmable logic device macrocell with an exclusive feedback line and an exclusive external input line | — | 1994-07-19 |
| 5300830 | Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control | — | 1994-04-05 |
| 5086290 | Mobile perimeter monitoring system | Shawn G. Murray | 1992-02-04 |