Issued Patents All Time
Showing 101–123 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7521322 | Vertical transistors | Sanh D. Tang | 2009-04-21 |
| 7501684 | Methods of forming semiconductor constructions | Sanh D. Tang, Kris K. Brown, Tuman Earl Allen, III | 2009-03-10 |
| 7419871 | Methods of forming semiconductor constructions | — | 2008-09-02 |
| 7416943 | Peripheral gate stacks and recessed array gates | Thomas A. Figura | 2008-08-26 |
| 7368344 | Methods of reducing floating body effect | — | 2008-05-06 |
| 7329924 | Integrated circuits and methods of forming a field effect transistor | Sanh D. Tang | 2008-02-12 |
| 7285812 | Vertical transistors | Sanh D. Tang | 2007-10-23 |
| 7271413 | Semiconductor constructions | Randal W. Chance, Sanh D. Tang, Steven D. Cummings | 2007-09-18 |
| 7244659 | Integrated circuits and methods of forming a field effect transistor | Sanh D. Tang | 2007-07-17 |
| 7214621 | Methods of forming devices associated with semiconductor constructions | Hasan Nejad, Thomas A. Figura, Ravi Iyer | 2007-05-08 |
| 7199419 | Memory structure for reduced floating body effect | — | 2007-04-03 |
| 7183164 | Methods of reducing floating body effect | — | 2007-02-27 |
| 7122425 | Methods of forming semiconductor constructions | Randal W. Chance, Sanh D. Tang, Steven D. Cummings | 2006-10-17 |
| 6927445 | Method to form a corrugated structure for enhanced capacitance | Randhir P. S. Thakur, Kirk D. Prall | 2005-08-09 |
| 6660611 | Method to form a corrugated structure for enhanced capacitance with plurality of boro-phospho silicate glass including germanium | Randhir P. S. Thakur, Kirk D. Prall | 2003-12-09 |
| 6469389 | Contact plug | Werner Juengling, Kirk D. Prall, David J. Keller, Tyler Lowrey | 2002-10-22 |
| 6346455 | Method to form a corrugated structure for enhanced capacitance | Randhir P. S. Thakur, Kirk D. Prall | 2002-02-12 |
| 6060783 | Self-aligned contact plugs | Werner Juengling, Kirk D. Prall, David J. Keller, Tyler Lowrey | 2000-05-09 |
| 5858865 | Method of forming contact plugs | Werner Juengling, Kirk D. Prall, David J. Keller, Tyler Lowrey | 1999-01-12 |
| 5804506 | Acceleration of etch selectivity for self-aligned contact | Randhir P. S. Thakur, Kirk D. Prall | 1998-09-08 |
| 5177027 | Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path | Tyler Lowrey, Randal W. Chance, D. Mark Durcan, Pierre C. Fazan, Fernando Gonzalez | 1993-01-05 |
| 5021353 | Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions | Tyler Lowrey, Dermot M. Durcan, Trung T. Doan, Mark E. Tuttle | 1991-06-04 |
| 5013680 | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography | Tyler Lowrey, Randal W. Chance, D. Mark Durcan, Ruojia Lee, Charles H. Dennison +3 more | 1991-05-07 |