Issued Patents All Time
Showing 26–50 of 338 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10614882 | Access signal adjustment circuits and methods for memory cells in a cross-point array | Chang Hua Siau | 2020-04-07 |
| 10453525 | Preservation circuit and methods to maintain values representing data in one or more layers of memory | Robert Norman | 2019-10-22 |
| 10354726 | Access signal adjustment circuits and methods for memory cells in a cross-point array | Chang Hua Siau | 2019-07-16 |
| 10347328 | SRAM with multiple power domains | Scott Hanson | 2019-07-09 |
| 10347332 | High voltage switching circuitry for a cross-point array | Chang Hua Siau | 2019-07-09 |
| 10340312 | Memory element with a reactive metal layer | Steve Kuo-Ren Hsia, Wayne Kinney, Steven W. Longcor, Darrell Rinerson, John Sanchez +2 more | 2019-07-02 |
| 10332589 | Method and apparatus for controlling substrate and well biases for reduced power requirements | Scott Hanson | 2019-06-25 |
| 10319429 | SRAM with error correction in retention mode | Stephen James Sheafor | 2019-06-11 |
| 10283185 | Write assist thyristor-based SRAM circuits and methods of operation | Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng | 2019-05-07 |
| 10224480 | Two-terminal reversibly switchable memory device | Darrell Rinerson, Wayne Kinney, Roy Lambertson, John Sanchez, Lawrence Schloss +2 more | 2019-03-05 |
| 10210917 | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory | Seow Fong Lim, Chang Hua Siau | 2019-02-19 |
| 10096354 | SRAM with error correction in retention mode | Stephen James Sheafor | 2018-10-09 |
| 10074420 | Access signal adjustment circuits and methods for memory cells in a cross-point array | Chang Hua Siau | 2018-09-11 |
| 10062431 | SRAM with multiple power domains | Scott Hanson | 2018-08-28 |
| 10056389 | Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication | Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng | 2018-08-21 |
| 10002646 | Local bit lines and methods of selecting the same to access memory elements in cross-point arrays | Chang Hua Siau, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala | 2018-06-19 |
| 9997241 | High voltage switching circuitry for a cross-point array | Chang Hua Siau | 2018-06-12 |
| 9899389 | Two-transistor SRAM semiconductor structure and methods of fabrication | Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng | 2018-02-20 |
| 9883465 | Determining transmit power based on categorization of access terminals | Cong Shen | 2018-01-30 |
| 9870809 | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory | Seow Fong Lim, Chang Hua Siau | 2018-01-16 |
| 9837149 | Low read current architecture for memory | Bruce L. Bateman, Darrell Rinerson, Chang Hua Siau | 2017-12-05 |
| 9831425 | Two-terminal reversibly switchable memory device | Darrell Rinerson, Wayne Kinney, Roy Lambertson, John Sanchez, Lawrence Schloss +2 more | 2017-11-28 |
| 9830974 | SRAM with active substrate bias | Scott Hanson | 2017-11-28 |
| 9830985 | Preservation circuit and methods to maintain values representing data in one or more layers of memory | Robert Norman | 2017-11-28 |
| 9806130 | Memory element with a reactive metal layer | Steve Kuo-Ren Hsia, Wayne Kinney, Steven W. Longcor, Darrell Rinerson, John Sanchez +2 more | 2017-10-31 |