Issued Patents All Time
Showing 276–295 of 295 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5234858 | Stacked surrounding wall capacitor | Pierre C. Fazan, Howard E. Rhodes, Yauh-Ching Liu | 1993-08-10 |
| 5232874 | Method for producing a semiconductor wafer having shallow and deep buried contacts | Howard E. Rhodes | 1993-08-03 |
| 5229326 | Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device | Guy T. Blalock | 1993-07-20 |
| 5219778 | Stacked V-cell capacitor | Ruojia Lee, Yauh-Ching Liu, Pierre C. Fazan | 1993-06-15 |
| 5206183 | Method of forming a bit line over capacitor array of memory cells | — | 1993-04-27 |
| 5198384 | Process for manufacturing a ferroelectric dynamic/non-volatile memory array using a disposable layer above storage-node junction | — | 1993-03-30 |
| 5196364 | Method of making a stacked capacitor dram cell | Pierre C. Fazan, Ruojia Lee, Yauh-Ching Liu | 1993-03-23 |
| 5170233 | Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor | Yauh-Ching Liu, Pierre C. Fazan, Hiang C. Chan, Howard E. Rhodes | 1992-12-08 |
| 5162248 | Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing | Michael A. Walker | 1992-11-10 |
| 5155057 | Stacked v-cell capacitor using a disposable composite dielectric on top of a digit line | Pierre C. Fazan, Ruojia Lee, Yauh-Ching Liu | 1992-10-13 |
| 5100826 | Process for manufacturing ultra-dense dynamic random access memories using partially-disposable dielectric filler strips between wordlines | — | 1992-03-31 |
| 5100825 | Method of making stacked surrounding reintrant wall capacitor | Pierre C. Fazan, Howard E. Rhodes, Yauh-Ching Liu | 1992-03-31 |
| 5100838 | Method for forming self-aligned conducting pillars in an (IC) fabrication process | — | 1992-03-31 |
| 5084406 | Method for forming low resistance DRAM digit-line | Howard E. Rhodes, Pierre C. Fazan, Hiang C. Chan, Yauh-Ching Liu | 1992-01-28 |
| 5061650 | Method for formation of a stacked capacitor | Hiang C. Chan, Yauh-Ching Liu, Pierre C. Fazan, Howard E. Rhodes | 1991-10-29 |
| 5053351 | Method of making stacked E-cell capacitor DRAM cell | Pierre C. Fazan, Hiang C. Chan, Howard E. Rhodes, Yauh-Ching Liu | 1991-10-01 |
| 5049517 | Method for formation of a stacked capacitor | Yauh-Ching Liu, Pierre C. Fazan, Hiang C. Chan, Howard E. Rhodes | 1991-09-17 |
| 5013680 | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography | Tyler Lowrey, Randal W. Chance, D. Mark Durcan, Ruojia Lee, Yauh-Ching Liu +3 more | 1991-05-07 |
| 4981810 | Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers | Pierre C. Fazan, Ruojia Lee, Yauh-Ching Liu | 1991-01-01 |
| 4965221 | Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions | Fernando Gonzalez | 1990-10-23 |