Issued Patents All Time
Showing 226–250 of 295 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5691547 | Planar thin film transistor structures | Monte Manning | 1997-11-25 |
| 5686747 | Integrated circuits comprising interconnecting plugs | Mark E. Jost, Kunal R. Parekh | 1997-11-11 |
| 5683927 | Method of forming CMOS integrated circuitry | Mark A. Helm | 1997-11-04 |
| 5663090 | Method to thermally form hemispherical grain (HSG) silicon to enhance capacitance for application in high density DRAMs | Randhir P. S. Thakur | 1997-09-02 |
| 5661045 | Method for forming and tailoring the electrical characteristics of semiconductor devices | Monte Manning, Howard E. Rhodes, Tyler Lowrey | 1997-08-26 |
| 5651855 | Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits | Trung T. Doan | 1997-07-29 |
| 5652164 | Semiconductor processing methods of forming stacked capacitors | Michael A. Walker | 1997-07-29 |
| 5650655 | Integrated circuitry having electrical interconnects | Monte Manning | 1997-07-22 |
| 5650350 | Semiconductor processing method of forming a static random access memory cell and static random access memory cell | Ken Marr | 1997-07-22 |
| 5637525 | Method of forming a CMOS circuitry | — | 1997-06-10 |
| 5624863 | Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate | Mark A. Helm | 1997-04-29 |
| 5616934 | Fully planarized thin film transistor (TFT) and process to fabricate same | Monte Manning | 1997-04-01 |
| 5605857 | Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells | Mark E. Jost | 1997-02-25 |
| 5563089 | Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells | Mark E. Jost, Kunal R. Parekh | 1996-10-08 |
| 5541137 | Method of forming improved contacts from polysilicon to silicon or other polysilicon layers | Monte Manning, Shubneesh Batra | 1996-07-30 |
| 5534449 | Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry | Mark A. Helm | 1996-07-09 |
| 5498562 | Semiconductor processing methods of forming stacked capacitors | Michael A. Walker | 1996-03-12 |
| 5494841 | Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells | Aftab Ahmad | 1996-02-27 |
| 5494851 | Semiconductor processing method of providing dopant impurity into a semiconductor substrate | Roger Lee | 1996-02-27 |
| 5493130 | Integrated circuitry having an electrically conductive sidewall link positioned over and electrically interconnecting respective outer sidewalls of two conductive layers | Monte Manning | 1996-02-20 |
| 5491356 | Capacitor structures for dynamic random access memory cells | Pierre C. Fazan | 1996-02-13 |
| 5489546 | Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process | Aftab Ahmad, Pierre C. Fazan | 1996-02-06 |
| 5434103 | Method of forming an electrical connection | Monte Manning | 1995-07-18 |
| 5411909 | Method of forming a planar thin film transistor | Monte Manning | 1995-05-02 |
| 5405788 | Method for forming and tailoring the electrical characteristics of semiconductor devices | Monte Manning, Howard E. Rhodes, Tyler Lowrey | 1995-04-11 |